118 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek mmsys controller8 9maintainers:10 - Matthias Brugger <matthias.bgg@gmail.com>11 12description:13 The MediaTek mmsys system controller provides clock control, routing control,14 and miscellaneous control in mmsys partition.15 16properties:17 $nodename:18 pattern: "^syscon@[0-9a-f]+$"19 20 compatible:21 oneOf:22 - items:23 - enum:24 - mediatek,mt2701-mmsys25 - mediatek,mt2712-mmsys26 - mediatek,mt6765-mmsys27 - mediatek,mt6779-mmsys28 - mediatek,mt6795-mmsys29 - mediatek,mt6797-mmsys30 - mediatek,mt8167-mmsys31 - mediatek,mt8173-mmsys32 - mediatek,mt8183-mmsys33 - mediatek,mt8186-mmsys34 - mediatek,mt8188-vdosys035 - mediatek,mt8188-vdosys136 - mediatek,mt8188-vppsys037 - mediatek,mt8188-vppsys138 - mediatek,mt8192-mmsys39 - mediatek,mt8195-vdosys140 - mediatek,mt8195-vppsys041 - mediatek,mt8195-vppsys142 - mediatek,mt8365-mmsys43 - const: syscon44 45 - description: vdosys0 and vdosys1 are 2 display HW pipelines,46 so mt8195 binding should be deprecated.47 deprecated: true48 items:49 - const: mediatek,mt8195-mmsys50 - const: syscon51 52 - items:53 - const: mediatek,mt7623-mmsys54 - const: mediatek,mt2701-mmsys55 - const: syscon56 57 - items:58 - const: mediatek,mt8195-vdosys059 - const: mediatek,mt8195-mmsys60 - const: syscon61 62 reg:63 maxItems: 164 65 power-domains:66 description:67 A phandle and PM domain specifier as defined by bindings68 of the power controller specified by phandle. See69 Documentation/devicetree/bindings/power/power-domain.yaml for details.70 71 mboxes:72 description:73 Using mailbox to communicate with GCE, it should have this74 property and list of phandle, mailbox specifiers. See75 Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml76 for details.77 $ref: /schemas/types.yaml#/definitions/phandle-array78 79 mediatek,gce-client-reg:80 description:81 The register of client driver can be configured by gce with 4 arguments82 defined in this property, such as phandle of gce, subsys id,83 register offset and size.84 Each subsys id is mapping to a base address of display function blocks85 register which is defined in the gce header86 include/dt-bindings/gce/<chip>-gce.h.87 $ref: /schemas/types.yaml#/definitions/phandle-array88 maxItems: 189 90 "#clock-cells":91 const: 192 93 '#reset-cells':94 const: 195 96required:97 - compatible98 - reg99 - "#clock-cells"100 101additionalProperties: false102 103examples:104 - |105 #include <dt-bindings/power/mt8173-power.h>106 #include <dt-bindings/gce/mt8173-gce.h>107 108 mmsys: syscon@14000000 {109 compatible = "mediatek,mt8173-mmsys", "syscon";110 reg = <0x14000000 0x1000>;111 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;112 #clock-cells = <1>;113 #reset-cells = <1>;114 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,115 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;116 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;117 };118