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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/arm/pmu.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ARM Performance Monitor Units8 9maintainers:10 - Mark Rutland <mark.rutland@arm.com>11 - Will Deacon <will.deacon@arm.com>12 13description: |+14 ARM cores often have a PMU for counting cpu and cache events like cache misses15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU16 representation in the device tree should be done as under:-17 18properties:19 compatible:20 items:21 - enum:22 - apm,potenza-pmu23 - apple,avalanche-pmu24 - apple,blizzard-pmu25 - apple,firestorm-pmu26 - apple,icestorm-pmu27 - arm,armv8-pmuv3 # Only for s/w models28 - arm,arm1136-pmu29 - arm,arm1176-pmu30 - arm,arm11mpcore-pmu31 - arm,cortex-a5-pmu32 - arm,cortex-a7-pmu33 - arm,cortex-a8-pmu34 - arm,cortex-a9-pmu35 - arm,cortex-a12-pmu36 - arm,cortex-a15-pmu37 - arm,cortex-a17-pmu38 - arm,cortex-a32-pmu39 - arm,cortex-a34-pmu40 - arm,cortex-a35-pmu41 - arm,cortex-a53-pmu42 - arm,cortex-a55-pmu43 - arm,cortex-a57-pmu44 - arm,cortex-a65-pmu45 - arm,cortex-a72-pmu46 - arm,cortex-a73-pmu47 - arm,cortex-a75-pmu48 - arm,cortex-a76-pmu49 - arm,cortex-a77-pmu50 - arm,cortex-a78-pmu51 - arm,cortex-a510-pmu52 - arm,cortex-a520-pmu53 - arm,cortex-a710-pmu54 - arm,cortex-a715-pmu55 - arm,cortex-a720-pmu56 - arm,cortex-a725-pmu57 - arm,cortex-x1-pmu58 - arm,cortex-x2-pmu59 - arm,cortex-x3-pmu60 - arm,cortex-x4-pmu61 - arm,cortex-x925-pmu62 - arm,neoverse-e1-pmu63 - arm,neoverse-n1-pmu64 - arm,neoverse-n2-pmu65 - arm,neoverse-n3-pmu66 - arm,neoverse-v1-pmu67 - arm,neoverse-v2-pmu68 - arm,neoverse-v3-pmu69 - arm,neoverse-v3ae-pmu70 - brcm,vulcan-pmu71 - cavium,thunder-pmu72 - nvidia,denver-pmu73 - nvidia,carmel-pmu74 - qcom,krait-pmu75 - qcom,scorpion-pmu76 - qcom,scorpion-mp-pmu77 78 interrupts:79 # Don't know how many CPUs, so no constraints to specify80 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.81 82 interrupt-affinity:83 $ref: /schemas/types.yaml#/definitions/phandle-array84 items:85 maxItems: 186 description:87 When using SPIs, specifies a list of phandles to CPU88 nodes corresponding directly to the affinity of89 the SPIs listed in the interrupts property.90 91 When using a PPI, specifies a list of phandles to CPU92 nodes corresponding to the set of CPUs which have93 a PMU of this type signalling the PPI listed in the94 interrupts property, unless this is already specified95 by the PPI interrupt specifier itself (in which case96 the interrupt-affinity property shouldn't be present).97 98 This property should be present when there is more than99 a single SPI.100 101 qcom,no-pc-write:102 type: boolean103 description:104 Indicates that this PMU doesn't support the 0xc and 0xd events.105 106 secure-reg-access:107 type: boolean108 description:109 Indicates that the ARMv7 Secure Debug Enable Register110 (SDER) is accessible. This will cause the driver to do111 any setup required that is only possible in ARMv7 secure112 state. If not present the ARMv7 SDER will not be touched,113 which means the PMU may fail to operate unless external114 code (bootloader or security monitor) has performed the115 appropriate initialisation. Note that this property is116 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux117 in Non-secure state.118 119required:120 - compatible121 122additionalProperties: false123 124...125