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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics STM32 ML-AHB interconnect8 9maintainers:10 - Fabien Dessenne <fabien.dessenne@foss.st.com>11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>12 13description: |14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory16 parts can be accessed through different addresses (see "RAM aliases" in [1])17 using different buses (see [2]): balancing the Cortex-M firmware accesses18 among those ports allows to tune the system performance.19 [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf20 [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping21 22allOf:23 - $ref: /schemas/simple-bus.yaml#24 25properties:26 compatible:27 contains:28 enum:29 - st,mlahb30 31 dma-ranges:32 description: |33 Describe memory addresses translation between the local CPU and the34 remote Cortex-M processor. Each memory region, is declared with35 3 parameters:36 - param 1: device base address (Cortex-M processor address)37 - param 2: physical base address (local CPU address)38 - param 3: size of the memory region.39 maxItems: 340 41 '#address-cells':42 const: 143 44 '#size-cells':45 const: 146 47required:48 - compatible49 - '#address-cells'50 - '#size-cells'51 - dma-ranges52 53unevaluatedProperties: false54 55examples:56 - |57 ahb {58 compatible = "st,mlahb", "simple-bus";59 #address-cells = <1>;60 #size-cells = <1>;61 ranges;62 dma-ranges = <0x00000000 0x38000000 0x10000>,63 <0x10000000 0x10000000 0x60000>,64 <0x30000000 0x30000000 0x60000>;65 66 m4_rproc: m4@10000000 {67 reg = <0x10000000 0x40000>;68 };69 };70 71...72