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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner Memory Bus (MBUS) controller8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13description: |14 The MBUS controller drives the MBUS that other devices in the SoC15 will use to perform DMA. It also has a register interface that16 allows to monitor and control the bandwidth and priorities for17 masters on that bus.18 19 Each device having to perform their DMA through the MBUS must have20 the interconnects and interconnect-names properties set to the MBUS21 controller and with "dma-mem" as the interconnect name.22 23properties:24 "#interconnect-cells":25 const: 126 description:27 The content of the cell is the MBUS ID.28 29 compatible:30 enum:31 - allwinner,sun5i-a13-mbus32 - allwinner,sun8i-a33-mbus33 - allwinner,sun8i-a50-mbus34 - allwinner,sun8i-a83t-mbus35 - allwinner,sun8i-h3-mbus36 - allwinner,sun8i-r40-mbus37 - allwinner,sun8i-v3s-mbus38 - allwinner,sun8i-v536-mbus39 - allwinner,sun20i-d1-mbus40 - allwinner,sun50i-a64-mbus41 - allwinner,sun50i-a100-mbus42 - allwinner,sun50i-h5-mbus43 - allwinner,sun50i-h6-mbus44 - allwinner,sun50i-h616-mbus45 - allwinner,sun50i-r329-mbus46 47 reg:48 minItems: 149 items:50 - description: MBUS interconnect/bandwidth limit/PMU registers51 - description: DRAM controller/PHY registers52 53 reg-names:54 minItems: 155 items:56 - const: mbus57 - const: dram58 59 clocks:60 minItems: 161 items:62 - description: MBUS interconnect module clock63 - description: DRAM controller/PHY module clock64 - description: Register bus clock, shared by MBUS and DRAM65 66 clock-names:67 minItems: 168 items:69 - const: mbus70 - const: dram71 - const: bus72 73 interrupts:74 maxItems: 175 description:76 MBUS PMU activity interrupt.77 78 dma-ranges:79 description:80 See section 2.3.9 of the DeviceTree Specification.81 82 '#address-cells': true83 84 '#size-cells': true85 86required:87 - "#interconnect-cells"88 - compatible89 - reg90 - clocks91 - dma-ranges92 93if:94 not:95 properties:96 compatible:97 contains:98 enum:99 - allwinner,sun5i-a13-mbus100 - allwinner,sun8i-r40-mbus101 102then:103 properties:104 reg:105 minItems: 2106 107 reg-names:108 minItems: 2109 110 clocks:111 minItems: 3112 113 clock-names:114 minItems: 3115 116 required:117 - reg-names118 - clock-names119 120else:121 properties:122 reg:123 maxItems: 1124 125 reg-names:126 maxItems: 1127 128 clocks:129 maxItems: 1130 131 clock-names:132 maxItems: 1133 134additionalProperties: false135 136examples:137 - |138 #include <dt-bindings/clock/sun50i-a64-ccu.h>139 #include <dt-bindings/interrupt-controller/arm-gic.h>140 141 dram-controller@1c01000 {142 compatible = "allwinner,sun5i-a13-mbus";143 reg = <0x01c01000 0x1000>;144 clocks = <&ccu CLK_MBUS>;145 #address-cells = <1>;146 #size-cells = <1>;147 dma-ranges = <0x00000000 0x40000000 0x20000000>;148 #interconnect-cells = <1>;149 };150 151 - |152 dram-controller@1c62000 {153 compatible = "allwinner,sun50i-a64-mbus";154 reg = <0x01c62000 0x1000>,155 <0x01c63000 0x1000>;156 reg-names = "mbus", "dram";157 clocks = <&ccu CLK_MBUS>,158 <&ccu CLK_DRAM>,159 <&ccu CLK_BUS_DRAM>;160 clock-names = "mbus", "dram", "bus";161 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;162 #address-cells = <1>;163 #size-cells = <1>;164 dma-ranges = <0x00000000 0x40000000 0xc0000000>;165 #interconnect-cells = <1>;166 };167 168...169