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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/ata/ahci-common.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Common Properties for Serial ATA AHCI controllers8 9maintainers:10 - Hans de Goede <hdegoede@redhat.com>11 - Damien Le Moal <dlemoal@kernel.org>12 13description:14 This document defines device tree properties for a common AHCI SATA15 controller implementation. It's hardware interface is supposed to16 conform to the technical standard defined by Intel (see Serial ATA17 Advanced Host Controller Interface specification for details). The18 document doesn't constitute a DT-node binding by itself but merely19 defines a set of common properties for the AHCI-compatible devices.20 21select: false22 23allOf:24 - $ref: sata-common.yaml#25 26properties:27 reg:28 description:29 Generic AHCI registers space conforming to the Serial ATA AHCI30 specification.31 32 reg-names:33 description: CSR space IDs34 contains:35 const: ahci36 37 interrupts:38 description:39 Generic AHCI state change interrupt. Can be implemented either as a40 single line attached to the controller or as a set of the signals41 indicating the particular port events.42 minItems: 143 maxItems: 3244 45 ahci-supply:46 description: Power regulator for AHCI controller47 48 target-supply:49 description: Power regulator for SATA target device50 51 phy-supply:52 description: Power regulator for SATA PHY53 54 phys:55 description: Reference to the SATA PHY node56 maxItems: 157 58 phy-names:59 const: sata-phy60 61 hba-cap:62 $ref: /schemas/types.yaml#/definitions/uint3263 description:64 Bitfield of the HBA generic platform capabilities like Staggered65 Spin-up or Mechanical Presence Switch support. It can be used to66 appropriately initialize the HWinit fields of the HBA CAP register67 in case if the system firmware hasn't done it.68 69 ports-implemented:70 $ref: /schemas/types.yaml#/definitions/uint3271 description:72 Mask that indicates which ports the HBA supports. Useful if PI is not73 programmed by the BIOS, which is true for some embedded SoC's.74 75patternProperties:76 "^sata-port@[0-9a-f]+$":77 $ref: '#/$defs/ahci-port'78 description:79 It is optionally possible to describe the ports as sub-nodes so80 to enable each port independently when dealing with multiple PHYs.81 82required:83 - reg84 - interrupts85 86additionalProperties: true87 88$defs:89 ahci-port:90 $ref: /schemas/ata/sata-common.yaml#/$defs/sata-port91 92 properties:93 reg:94 description:95 AHCI SATA port identifier. By design AHCI controller can't have96 more than 32 ports due to the CAP.NP fields and PI register size97 constraints.98 minimum: 099 maximum: 31100 101 phys:102 description: Individual AHCI SATA port PHY103 maxItems: 1104 105 phy-names:106 description: AHCI SATA port PHY ID107 const: sata-phy108 109 target-supply:110 description: Power regulator for SATA port target device111 112 hba-port-cap:113 $ref: /schemas/types.yaml#/definitions/uint32114 description:115 Bitfield of the HBA port-specific platform capabilities like Hot116 plugging, eSATA, FIS-based Switching, etc (see AHCI specification117 for details). It can be used to initialize the HWinit fields of118 the PxCMD register in case if the system firmware hasn't done it.119 120 required:121 - reg122 123...124