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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: AHCI SATA Controller8 9description: |10 SATA nodes are defined to describe on-chip Serial ATA controllers.11 Each SATA controller should have its own node.12 13 It is possible, but not required, to represent each port as a sub-node.14 It allows to enable each port independently when dealing with multiple15 PHYs.16 17maintainers:18 - Hans de Goede <hdegoede@redhat.com>19 - Jens Axboe <axboe@kernel.dk>20 21select:22 properties:23 compatible:24 contains:25 enum:26 - brcm,iproc-ahci27 - cavium,octeon-7130-ahci28 - hisilicon,hisi-ahci29 - ibm,476gtr-ahci30 - marvell,armada-3700-ahci31 - marvell,armada-8k-ahci32 - marvell,berlin2q-ahci33 - qcom,apq8064-ahci34 - qcom,ipq806x-ahci35 - socionext,uniphier-pro4-ahci36 - socionext,uniphier-pxs2-ahci37 - socionext,uniphier-pxs3-ahci38 required:39 - compatible40 41properties:42 compatible:43 oneOf:44 - items:45 - enum:46 - brcm,iproc-ahci47 - marvell,armada-8k-ahci48 - marvell,berlin2-ahci49 - marvell,berlin2q-ahci50 - qcom,apq8064-ahci51 - qcom,ipq806x-ahci52 - socionext,uniphier-pro4-ahci53 - socionext,uniphier-pxs2-ahci54 - socionext,uniphier-pxs3-ahci55 - const: generic-ahci56 - enum:57 - cavium,octeon-7130-ahci58 - hisilicon,hisi-ahci59 - ibm,476gtr-ahci60 - marvell,armada-3700-ahci61 62 reg:63 minItems: 164 maxItems: 265 66 reg-names:67 maxItems: 168 69 clocks:70 minItems: 171 maxItems: 572 73 clock-names:74 minItems: 175 maxItems: 576 77 interrupts:78 maxItems: 179 80 power-domains:81 maxItems: 182 83 resets:84 minItems: 185 maxItems: 386 87patternProperties:88 "^sata-port@[0-9a-f]+$":89 $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port90 91 anyOf:92 - required: [ phys ]93 - required: [ target-supply ]94 95 unevaluatedProperties: false96 97required:98 - compatible99 - reg100 - interrupts101 102allOf:103 - $ref: ahci-common.yaml#104 105 - if:106 properties:107 compatible:108 contains:109 enum:110 - qcom,apq8064-ahci111 - qcom,ipq806x-ahci112 then:113 properties:114 clocks:115 minItems: 5116 clock-names:117 items:118 - const: slave_iface119 - const: iface120 - const: core121 - const: rxoob122 - const: pmalive123 required:124 - phys125 - phy-names126 - clocks127 - clock-names128 129 - if:130 properties:131 compatible:132 contains:133 const: socionext,uniphier-pro4-ahci134 then:135 properties:136 resets:137 items:138 - description: reset line for the parent139 - description: reset line for the glue logic140 - description: reset line for the controller141 required:142 - resets143 else:144 if:145 properties:146 compatible:147 contains:148 enum:149 - socionext,uniphier-pxs2-ahci150 - socionext,uniphier-pxs3-ahci151 then:152 properties:153 resets:154 items:155 - description: reset for the glue logic156 - description: reset for the controller157 required:158 - resets159 else:160 properties:161 resets:162 maxItems: 1163 164unevaluatedProperties: false165 166examples:167 - |168 sata@ffe08000 {169 compatible = "snps,spear-ahci";170 reg = <0xffe08000 0x1000>;171 interrupts = <115>;172 };173 - |174 #include <dt-bindings/interrupt-controller/arm-gic.h>175 #include <dt-bindings/clock/berlin2q.h>176 #include <dt-bindings/ata/ahci.h>177 178 sata@f7e90000 {179 compatible = "marvell,berlin2q-ahci", "generic-ahci";180 reg = <0xf7e90000 0x1000>;181 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;182 clocks = <&chip CLKID_SATA>;183 #address-cells = <1>;184 #size-cells = <0>;185 186 hba-cap = <HBA_SMPS>;187 188 sata0: sata-port@0 {189 reg = <0>;190 191 phys = <&sata_phy 0>;192 target-supply = <®_sata0>;193 194 hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;195 };196 197 sata1: sata-port@1 {198 reg = <1>;199 200 phys = <&sata_phy 1>;201 target-supply = <®_sata1>;202 203 hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;204 };205 };206