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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Calxeda AHCI SATA Controller8 9description: |10 The Calxeda SATA controller mostly conforms to the AHCI interface11 with some special extensions to add functionality, to map GPIOs for12 activity LEDs and for mapping the ComboPHYs.13 14maintainers:15 - Andre Przywara <andre.przywara@arm.com>16 17properties:18 compatible:19 const: calxeda,hb-ahci20 21 reg:22 maxItems: 123 24 interrupts:25 maxItems: 126 27 dma-coherent: true28 29 calxeda,pre-clocks:30 $ref: /schemas/types.yaml#/definitions/uint3231 description: |32 Indicates the number of additional clock cycles to transmit before33 sending an SGPIO pattern.34 35 calxeda,post-clocks:36 $ref: /schemas/types.yaml#/definitions/uint3237 description: |38 Indicates the number of additional clock cycles to transmit after39 sending an SGPIO pattern.40 41 calxeda,led-order:42 description: Maps port numbers to offsets within the SGPIO bitstream.43 $ref: /schemas/types.yaml#/definitions/uint32-array44 minItems: 145 maxItems: 846 47 calxeda,port-phys:48 description: |49 phandle-combophy and lane assignment, which maps each SATA port to a50 combophy and a lane within that combophy51 $ref: /schemas/types.yaml#/definitions/phandle-array52 minItems: 153 maxItems: 854 items:55 maxItems: 256 57 calxeda,tx-atten:58 description: |59 Contains TX attenuation override codes, one per port.60 The upper 24 bits of each entry are always 0 and thus ignored.61 $ref: /schemas/types.yaml#/definitions/uint32-array62 minItems: 163 maxItems: 864 65 calxeda,sgpio-gpio:66 maxItems: 367 description: |68 phandle-gpio bank, bit offset, and default on or off, which indicates69 that the driver supports SGPIO indicator lights using the indicated70 GPIOs.71 72required:73 - compatible74 - reg75 - interrupts76 77additionalProperties: false78 79examples:80 - |81 sata@ffe08000 {82 compatible = "calxeda,hb-ahci";83 reg = <0xffe08000 0x1000>;84 interrupts = <115>;85 dma-coherent;86 calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,87 <&combophy0 2>, <&combophy0 3>;88 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;89 calxeda,led-order = <4 0 1 2 3>;90 calxeda,tx-atten = <0xff 22 0xff 0xff 23>;91 calxeda,pre-clocks = <10>;92 calxeda,post-clocks = <0>;93 };94 95...96