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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Synopsys DWC AHCI SATA controller properties8 9maintainers:10 - Serge Semin <fancer.lancer@gmail.com>11 12description:13 This document defines device tree schema for the generic Synopsys DWC14 AHCI controller properties.15 16select: false17 18allOf:19 - $ref: ahci-common.yaml#20 21properties:22 reg:23 maxItems: 124 25 interrupts:26 maxItems: 127 28 clocks:29 description:30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)32 clock, etc.33 minItems: 134 maxItems: 635 36 clock-names:37 minItems: 138 maxItems: 639 items:40 oneOf:41 - description: Application APB/AHB/AXI BIU clock42 enum:43 - pclk44 - aclk45 - hclk46 - sata47 - description: Power Module keep-alive clock48 const: pmalive49 - description: RxOOB detection clock50 const: rxoob51 - description: PHY Transmit Clock52 const: asic53 - description: PHY Receive Clock54 const: rbc55 - description: SATA Ports reference clock56 const: ref57 58 resets:59 description:60 At least basic application and reference clock domains resets are61 normally supported by the DWC AHCI SATA controller.62 minItems: 163 maxItems: 464 65 reset-names:66 minItems: 167 maxItems: 468 items:69 oneOf:70 - description: Application AHB/AXI BIU clock domain reset control71 enum:72 - arst73 - hrst74 - description: Power Module keep-alive clock domain reset control75 const: pmalive76 - description: RxOOB detection clock domain reset control77 const: rxoob78 - description: Reference clock domain reset control79 const: ref80 81patternProperties:82 "^sata-port@[0-9a-e]$":83 $ref: '#/$defs/dwc-ahci-port'84 85additionalProperties: true86 87$defs:88 dwc-ahci-port:89 $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port90 91 properties:92 reg:93 minimum: 094 maximum: 795 96 snps,tx-ts-max:97 $ref: /schemas/types.yaml#/definitions/uint3298 description: Maximal size of Tx DMA transactions in FIFO words99 enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]100 101 snps,rx-ts-max:102 $ref: /schemas/types.yaml#/definitions/uint32103 description: Maximal size of Rx DMA transactions in FIFO words104 enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]105 106...107