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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC3%YAML 1.24---5$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Baikal-T1 AXI-bus9 10maintainers:11 - Serge Semin <fancer.lancer@gmail.com>12 13description: |14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all15 high-speed peripheral IP-cores with RAM controller and with MIPS P560016 cores. Traffic arbitration is done by means of DW AXI Interconnect (so17 called AXI Main Interconnect) routing IO requests from one block to18 another: from CPU to SoC peripherals and between some SoC peripherals19 (mostly between peripheral devices and RAM, but also between DMA and20 some peripherals). In case of any protocol error, device not responding21 an IRQ is raised and a faulty situation is reported to the AXI EHB22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and23 accessible by means of the Baikal-T1 System Controller.24 25allOf:26 - $ref: /schemas/simple-bus.yaml#27 28properties:29 compatible:30 contains:31 const: baikal,bt1-axi32 33 reg:34 minItems: 135 items:36 - description: Synopsys DesignWare AXI Interconnect QoS registers37 - description: AXI EHB MMIO system controller registers38 39 reg-names:40 minItems: 141 items:42 - const: qos43 - const: ehb44 45 '#interconnect-cells':46 const: 147 48 syscon:49 $ref: /schemas/types.yaml#/definitions/phandle50 description: Phandle to the Baikal-T1 System Controller DT node51 52 interrupts:53 maxItems: 154 55 clocks:56 items:57 - description: Main Interconnect uplink reference clock58 59 clock-names:60 items:61 - const: aclk62 63 resets:64 items:65 - description: Main Interconnect reset line66 67 reset-names:68 items:69 - const: arst70 71unevaluatedProperties: false72 73required:74 - compatible75 - reg76 - reg-names77 - syscon78 - interrupts79 - clocks80 - clock-names81 82examples:83 - |84 #include <dt-bindings/interrupt-controller/mips-gic.h>85 86 bus@1f05a000 {87 compatible = "baikal,bt1-axi", "simple-bus";88 reg = <0x1f05a000 0x1000>,89 <0x1f04d110 0x8>;90 reg-names = "qos", "ehb";91 #address-cells = <1>;92 #size-cells = <1>;93 #interconnect-cells = <1>;94 95 syscon = <&syscon>;96 97 ranges;98 99 interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;100 101 clocks = <&ccu_axi 0>;102 clock-names = "aclk";103 104 resets = <&ccu_axi 0>;105 reset-names = "arst";106 };107...108