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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STM32 Resource isolation framework security controller8 9maintainers:10 - Gatien Chevallier <gatien.chevallier@foss.st.com>11 12description: |13 Resource isolation framework (RIF) is a comprehensive set of hardware blocks14 designed to enforce and manage isolation of STM32 hardware resources like15 memory and peripherals.16 17 The RIFSC (RIF security controller) is composed of three sets of registers,18 each managing a specific set of hardware resources:19 - RISC registers associated with RISUP logic (resource isolation device unit20 for peripherals), assign all non-RIF aware peripherals to zero, one or21 any security domains (secure, privilege, compartment).22 - RIMC registers: associated with RIMU logic (resource isolation master23 unit), assign all non RIF-aware bus master to one security domain by24 setting secure, privileged and compartment information on the system bus.25 Alternatively, the RISUP logic controlling the device port access to a26 peripheral can assign target bus attributes to this peripheral master port27 (supported attribute: CID).28 - RISC registers associated with RISAL logic (resource isolation device unit29 for address space - Lite version), assign address space subregions to one30 security domains (secure, privilege, compartment).31 32select:33 properties:34 compatible:35 contains:36 const: st,stm32mp25-rifsc37 required:38 - compatible39 40properties:41 compatible:42 items:43 - const: st,stm32mp25-rifsc44 - const: simple-bus45 46 reg:47 maxItems: 148 49 "#address-cells":50 const: 151 52 "#size-cells":53 const: 154 55 ranges: true56 57 "#access-controller-cells":58 const: 159 description:60 Contains the firewall ID associated to the peripheral.61 62patternProperties:63 "^.*@[0-9a-f]+$":64 description: Peripherals65 type: object66 67 additionalProperties: true68 69 required:70 - access-controllers71 72required:73 - compatible74 - reg75 - "#address-cells"76 - "#size-cells"77 - "#access-controller-cells"78 - ranges79 80additionalProperties: false81 82examples:83 - |84 // In this example, the usart2 device refers to rifsc as its domain85 // controller.86 // Access rights are verified before creating devices.87 88 #include <dt-bindings/interrupt-controller/arm-gic.h>89 90 rifsc: bus@42080000 {91 compatible = "st,stm32mp25-rifsc", "simple-bus";92 reg = <0x42080000 0x1000>;93 #address-cells = <1>;94 #size-cells = <1>;95 #access-controller-cells = <1>;96 ranges;97 98 usart2: serial@400e0000 {99 compatible = "st,stm32h7-uart";100 reg = <0x400e0000 0x400>;101 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;102 clocks = <&ck_flexgen_08>;103 access-controllers = <&rifsc 32>;104 };105 };106