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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/bus/ti-sysc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Texas Instruments interconnect target module8 9maintainers:10 - Tony Lindgren <tony@atomide.com>11 12description:13 Texas Instruments SoCs can have a generic interconnect target module14 for devices connected to various interconnects such as L3 interconnect15 using Arteris NoC, and L4 interconnect using Sonics s3220. This module16 is mostly used for interaction between module and Power, Reset and Clock17 Manager PRCM. It participates in the OCP Disconnect Protocol, but other18 than that it is mostly independent of the interconnect.19 20 Each interconnect target module can have one or more devices connected to21 it. There is a set of control registers for managing the interconnect target22 module clocks, idle modes and interconnect level resets.23 24 The interconnect target module control registers are sprinkled into the25 unused register address space of the first child device IP block managed by26 the interconnect target module. Typically the register names are REVISION,27 SYSCONFIG and SYSSTATUS.28 29properties:30 $nodename:31 pattern: "^target-module(@[0-9a-f]+)?$"32 33 compatible:34 oneOf:35 - items:36 - enum:37 - ti,sysc-omap238 - ti,sysc-omap439 - ti,sysc-omap4-simple40 - ti,sysc-omap2-timer41 - ti,sysc-omap4-timer42 - ti,sysc-omap3430-sr43 - ti,sysc-omap3630-sr44 - ti,sysc-omap4-sr45 - ti,sysc-omap3-sham46 - ti,sysc-omap-aes47 - ti,sysc-mcasp48 - ti,sysc-dra7-mcasp49 - ti,sysc-usb-host-fs50 - ti,sysc-dra7-mcan51 - ti,sysc-pruss52 - const: ti,sysc53 - items:54 - const: ti,sysc55 56 reg:57 description:58 Interconnect target module control registers consisting of59 REVISION, SYSCONFIG and SYSSTATUS registers as defined in the60 Technical Reference Manual for the SoC.61 minItems: 162 maxItems: 363 64 reg-names:65 description:66 Interconnect target module control register names consisting67 of "rev", "sysc" and "syss".68 oneOf:69 - minItems: 170 items:71 - const: rev72 - const: sysc73 - const: syss74 - items:75 - const: rev76 - const: syss77 - enum: [ sysc, syss ]78 79 power-domains:80 description: Target module power domain if available.81 maxItems: 182 83 clocks:84 description:85 Target module clocks consisting of one functional clock, one86 interface clock, and up to 8 module specific optional clocks.87 Some modules may have only the functional clock, and some have88 no configurable clocks.89 minItems: 190 maxItems: 491 92 clock-names:93 description:94 Target module clock names like "fck", "ick", "optck1", "optck2"95 if the clocks are configurable.96 oneOf:97 - enum: [ ick, fck, sys_clk ]98 - items:99 - const: fck100 - enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ]101 - items:102 - const: fck103 - const: phy-clk104 - const: phy-clk-div105 - items:106 - const: fck107 - const: hdmi_clk108 - const: sys_clk109 - const: tv_clk110 - items:111 - const: fck112 - const: ahclkx113 - const: ahclkr114 115 resets:116 description:117 Target module reset bit in the RSTCTRL register if wired for the module.118 Note that the other reset bits should be mapped for the child device119 driver to use.120 maxItems: 1121 122 reset-names:123 description:124 Target module reset names in the RSTCTRL register, typically named125 "rstctrl" if only one reset bit is wired for the module.126 items:127 - const: rstctrl128 129 '#address-cells':130 enum: [ 1, 2 ]131 132 '#size-cells':133 enum: [ 1, 2 ]134 135 ranges: true136 137 dma-ranges: true138 139 ti,sysc-mask:140 description: Mask of supported register bits for the SYSCONFIG register141 $ref: /schemas/types.yaml#/definitions/uint32142 143 ti,sysc-midle:144 description: List of hardware supported idle modes145 $ref: /schemas/types.yaml#/definitions/uint32-array146 147 ti,sysc-sidle:148 description: List of hardware supported idle modes149 $ref: /schemas/types.yaml#/definitions/uint32-array150 151 ti,syss-mask:152 description: Mask of supported register bits for the SYSSTATUS register153 $ref: /schemas/types.yaml#/definitions/uint32154 155 ti,sysc-delay-us:156 description: Delay needed after OCP softreset before accessing SYCONFIG157 default: 0158 minimum: 0159 maximum: 2160 161 ti,no-reset-on-init:162 description: Interconnect target module shall not be reset at init163 type: boolean164 165 ti,no-idle-on-init:166 description: Interconnect target module shall not be idled at init167 type: boolean168 169 ti,no-idle:170 description: Interconnect target module shall not be idled171 type: boolean172 173 ti,hwmods:174 description: Interconnect module name to use with legacy hwmod data175 $ref: /schemas/types.yaml#/definitions/string176 deprecated: true177 178required:179 - compatible180 - '#address-cells'181 - '#size-cells'182 - ranges183 184additionalProperties:185 type: object186 187examples:188 - |189 #include <dt-bindings/bus/ti-sysc.h>190 #include <dt-bindings/clock/omap4.h>191 192 target-module@2b000 {193 compatible = "ti,sysc-omap2", "ti,sysc";194 ti,hwmods = "usb_otg_hs";195 reg = <0x2b400 0x4>,196 <0x2b404 0x4>,197 <0x2b408 0x4>;198 reg-names = "rev", "sysc", "syss";199 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;200 clock-names = "fck";201 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |202 SYSC_OMAP2_SOFTRESET |203 SYSC_OMAP2_AUTOIDLE)>;204 ti,sysc-midle = <SYSC_IDLE_FORCE>,205 <SYSC_IDLE_NO>,206 <SYSC_IDLE_SMART>;207 ti,sysc-sidle = <SYSC_IDLE_FORCE>,208 <SYSC_IDLE_NO>,209 <SYSC_IDLE_SMART>,210 <SYSC_IDLE_SMART_WKUP>;211 ti,syss-mask = <1>;212 #address-cells = <1>;213 #size-cells = <1>;214 ranges = <0 0x2b000 0x1000>;215 };216