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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright (C) 2023 Renesas Electronics Corp.3%YAML 1.24---5$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Andestech AX45MP L2 Cache Controller9 10maintainers:11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>12 13description:14 A level-2 cache (L2C) is used to improve the system performance by providing15 a large amount of cache line entries and reasonable access delays. The L2C16 is shared between cores, and a non-inclusive non-exclusive policy is used.17 18select:19 properties:20 compatible:21 contains:22 enum:23 - andestech,ax45mp-cache24 25 required:26 - compatible27 28properties:29 compatible:30 items:31 - const: andestech,ax45mp-cache32 - const: cache33 34 reg:35 maxItems: 136 37 interrupts:38 maxItems: 139 40 cache-line-size:41 const: 6442 43 cache-level:44 const: 245 46 cache-sets:47 const: 102448 49 cache-size:50 enum: [131072, 262144, 524288, 1048576, 2097152]51 52 cache-unified: true53 54 next-level-cache: true55 56additionalProperties: false57 58required:59 - compatible60 - reg61 - interrupts62 - cache-line-size63 - cache-level64 - cache-sets65 - cache-size66 - cache-unified67 68examples:69 - |70 #include <dt-bindings/interrupt-controller/irq.h>71 72 cache-controller@13400000 {73 compatible = "andestech,ax45mp-cache", "cache";74 reg = <0x13400000 0x100000>;75 interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;76 cache-line-size = <64>;77 cache-level = <2>;78 cache-sets = <1024>;79 cache-size = <262144>;80 cache-unified;81 };82