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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC3%YAML 1.24---5$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Baikal-T1 L2-cache Control Block9 10maintainers:11 - Serge Semin <fancer.lancer@gmail.com>12 13description: |14 By means of the System Controller Baikal-T1 SoC exposes a few settings to15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T117 L2-cache controller block is responsible for the tuning. Its DT node is18 supposed to be a child of the system controller.19 20properties:21 compatible:22 const: baikal,bt1-l2-ctl23 24 reg:25 maxItems: 126 27 baikal,l2-ws-latency:28 $ref: /schemas/types.yaml#/definitions/uint3229 description: Cycles of latency for Way-select RAM accesses30 default: 031 minimum: 032 maximum: 333 34 baikal,l2-tag-latency:35 $ref: /schemas/types.yaml#/definitions/uint3236 description: Cycles of latency for Tag RAM accesses37 default: 038 minimum: 039 maximum: 340 41 baikal,l2-data-latency:42 $ref: /schemas/types.yaml#/definitions/uint3243 description: Cycles of latency for Data RAM accesses44 default: 145 minimum: 046 maximum: 347 48additionalProperties: false49 50required:51 - compatible52 53examples:54 - |55 l2@1f04d028 {56 compatible = "baikal,bt1-l2-ctl";57 reg = <0x1f04d028 0x004>;58 59 baikal,l2-ws-latency = <1>;60 baikal,l2-tag-latency = <1>;61 baikal,l2-data-latency = <2>;62 };63...64