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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: ARM L2 Cache Controller8 9maintainers:10 - Rob Herring <robh@kernel.org>11 12description: |+13 ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/14 PL220/PL310 and variants) based level 2 cache controller. All these various15 implementations of the L2 cache controller have compatible programming16 models (Note 1). Some of the properties that are just prefixed "cache-*" are17 taken from section 3.7.3 of the Devicetree Specification which can be found18 at:19 https://www.devicetree.org/specifications/20 21 Note 1: The description in this document doesn't apply to integrated L222 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These23 integrated L2 controllers are assumed to be all preconfigured by24 early secure boot code. Thus no need to deal with their configuration25 in the kernel at all.26 27allOf:28 - $ref: /schemas/cache-controller.yaml#29 30properties:31 compatible:32 oneOf:33 - enum:34 - arm,pl310-cache35 - arm,l220-cache36 - arm,l210-cache37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"38 - bcm,bcm11351-a2-pl310-cache39 # For Broadcom bcm11351 chipset where an40 # offset needs to be added to the address before passing down to the L241 # cache controller42 - brcm,bcm11351-a2-pl310-cache43 # Marvell Controller designed to be44 # compatible with the ARM one, with system cache mode (meaning45 # maintenance operations on L1 are broadcasted to the L2 and L246 # performs the same operation).47 - marvell,aurora-system-cache48 # Marvell Controller designed to be49 # compatible with the ARM one with outer cache mode.50 - marvell,aurora-outer-cache51 - items:52 # Marvell Tauros3 cache controller, compatible53 # with arm,pl310-cache controller.54 - const: marvell,tauros3-cache55 - const: arm,pl310-cache56 57 cache-level:58 const: 259 60 cache-unified: true61 cache-size: true62 cache-sets: true63 cache-block-size: true64 cache-line-size: true65 66 reg:67 maxItems: 168 69 arm,data-latency:70 description: Cycles of latency for Data RAM accesses. Specifies 3 cells of71 read, write and setup latencies. Minimum valid values are 1. Controllers72 without setup latency control should use a value of 0.73 $ref: /schemas/types.yaml#/definitions/uint32-array74 minItems: 275 maxItems: 376 items:77 minimum: 078 maximum: 879 80 arm,tag-latency:81 description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of82 read, write and setup latencies. Controllers without setup latency control83 should use 0. Controllers without separate read and write Tag RAM latency84 values should only use the first cell.85 $ref: /schemas/types.yaml#/definitions/uint32-array86 minItems: 187 maxItems: 388 items:89 minimum: 090 maximum: 891 92 arm,dirty-latency:93 description: Cycles of latency for Dirty RAMs. This is a single cell.94 $ref: /schemas/types.yaml#/definitions/uint3295 minimum: 196 maximum: 897 98 arm,filter-ranges:99 description: <start length> Starting address and length of window to100 filter. Addresses in the filter window are directed to the M1 port. Other101 addresses will go to the M0 port.102 $ref: /schemas/types.yaml#/definitions/uint32-array103 items:104 minItems: 2105 maxItems: 2106 107 arm,io-coherent:108 description: indicates that the system is operating in an hardware109 I/O coherent mode. Valid only when the arm,pl310-cache compatible110 string is used.111 type: boolean112 113 interrupts:114 # Either a single combined interrupt or up to 9 individual interrupts115 minItems: 1116 maxItems: 9117 118 cache-id-part:119 description: cache id part number to be used if it is not present120 on hardware121 $ref: /schemas/types.yaml#/definitions/uint32122 123 wt-override:124 description: If present then L2 is forced to Write through mode125 type: boolean126 127 arm,double-linefill:128 description: Override double linefill enable setting. Enable if129 non-zero, disable if zero.130 $ref: /schemas/types.yaml#/definitions/uint32131 enum: [0, 1]132 133 arm,double-linefill-incr:134 description: Override double linefill on INCR read. Enable135 if non-zero, disable if zero.136 $ref: /schemas/types.yaml#/definitions/uint32137 enum: [0, 1]138 139 arm,double-linefill-wrap:140 description: Override double linefill on WRAP read. Enable141 if non-zero, disable if zero.142 $ref: /schemas/types.yaml#/definitions/uint32143 enum: [0, 1]144 145 arm,prefetch-drop:146 description: Override prefetch drop enable setting. Enable if non-zero,147 disable if zero.148 $ref: /schemas/types.yaml#/definitions/uint32149 enum: [0, 1]150 151 arm,prefetch-offset:152 description: Override prefetch offset value.153 $ref: /schemas/types.yaml#/definitions/uint32154 enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]155 156 arm,shared-override:157 description: The default behavior of the L220 or PL310 cache158 controllers with respect to the shareable attribute is to transform "normal159 memory non-cacheable transactions" into "cacheable no allocate" (for reads)160 or "write through no write allocate" (for writes).161 On systems where this may cause DMA buffer corruption, this property must162 be specified to indicate that such transforms are precluded.163 type: boolean164 165 arm,parity-enable:166 description: enable parity checking on the L2 cache (L220 or PL310).167 type: boolean168 169 arm,parity-disable:170 description: disable parity checking on the L2 cache (L220 or PL310).171 type: boolean172 173 marvell,ecc-enable:174 description: enable ECC protection on the L2 cache175 type: boolean176 177 arm,outer-sync-disable:178 description: disable the outer sync operation on the L2 cache.179 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that180 will randomly hang unless outer sync operations are disabled.181 type: boolean182 183 prefetch-data:184 description: |185 Data prefetch. Value: <0> (forcibly disable), <1>186 (forcibly enable), property absent (retain settings set by firmware)187 $ref: /schemas/types.yaml#/definitions/uint32188 enum: [0, 1]189 190 prefetch-instr:191 description: |192 Instruction prefetch. Value: <0> (forcibly disable),193 <1> (forcibly enable), property absent (retain settings set by194 firmware)195 $ref: /schemas/types.yaml#/definitions/uint32196 enum: [0, 1]197 198 arm,dynamic-clock-gating:199 description: |200 L2 dynamic clock gating. Value: <0> (forcibly201 disable), <1> (forcibly enable), property absent (OS specific behavior,202 preferably retain firmware settings)203 $ref: /schemas/types.yaml#/definitions/uint32204 enum: [0, 1]205 206 arm,standby-mode:207 description: L2 standby mode enable. Value <0> (forcibly disable),208 <1> (forcibly enable), property absent (OS specific behavior,209 preferably retain firmware settings)210 $ref: /schemas/types.yaml#/definitions/uint32211 enum: [0, 1]212 213 arm,early-bresp-disable:214 description: Disable the CA9 optimization Early BRESP (PL310)215 type: boolean216 217 arm,full-line-zero-disable:218 description: Disable the CA9 optimization Full line of zero219 write (PL310)220 type: boolean221 222required:223 - compatible224 - cache-unified225 - reg226 227additionalProperties: false228 229examples:230 - |231 cache-controller@fff12000 {232 compatible = "arm,pl310-cache";233 reg = <0xfff12000 0x1000>;234 arm,data-latency = <1 1 1>;235 arm,tag-latency = <2 2 2>;236 arm,filter-ranges = <0x80000000 0x8000000>;237 cache-unified;238 cache-level = <2>;239 interrupts = <45>;240 };241 242...243