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1# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Last Level Cache Controller8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 12description: |13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,14 that can be shared by multiple clients. Clients here are different cores in the15 SoC, the idea is to minimize the local caches at the clients and migrate to16 common pool of memory. Cache memory is divided into partitions called slices17 which are assigned to clients. Clients can query the slice details, activate18 and deactivate them.19 20properties:21 compatible:22 enum:23 - qcom,qdu1000-llcc24 - qcom,sa8775p-llcc25 - qcom,sc7180-llcc26 - qcom,sc7280-llcc27 - qcom,sc8180x-llcc28 - qcom,sc8280xp-llcc29 - qcom,sdm845-llcc30 - qcom,sm6350-llcc31 - qcom,sm7150-llcc32 - qcom,sm8150-llcc33 - qcom,sm8250-llcc34 - qcom,sm8350-llcc35 - qcom,sm8450-llcc36 - qcom,sm8550-llcc37 - qcom,sm8650-llcc38 - qcom,x1e80100-llcc39 40 reg:41 minItems: 242 maxItems: 943 44 reg-names:45 minItems: 246 maxItems: 947 48 interrupts:49 maxItems: 150 51 nvmem-cells:52 items:53 - description: Reference to an nvmem node for multi channel DDR54 55 nvmem-cell-names:56 items:57 - const: multi-chan-ddr58 59required:60 - compatible61 - reg62 - reg-names63 64allOf:65 - if:66 properties:67 compatible:68 contains:69 enum:70 - qcom,sc7180-llcc71 - qcom,sm6350-llcc72 then:73 properties:74 reg:75 items:76 - description: LLCC0 base register region77 - description: LLCC broadcast base register region78 reg-names:79 items:80 - const: llcc0_base81 - const: llcc_broadcast_base82 83 - if:84 properties:85 compatible:86 contains:87 enum:88 - qcom,sa8775p-llcc89 then:90 properties:91 reg:92 items:93 - description: LLCC0 base register region94 - description: LLCC1 base register region95 - description: LLCC2 base register region96 - description: LLCC3 base register region97 - description: LLCC4 base register region98 - description: LLCC5 base register region99 - description: LLCC broadcast base register region100 reg-names:101 items:102 - const: llcc0_base103 - const: llcc1_base104 - const: llcc2_base105 - const: llcc3_base106 - const: llcc4_base107 - const: llcc5_base108 - const: llcc_broadcast_base109 110 - if:111 properties:112 compatible:113 contains:114 enum:115 - qcom,sc7280-llcc116 then:117 properties:118 reg:119 items:120 - description: LLCC0 base register region121 - description: LLCC1 base register region122 - description: LLCC broadcast base register region123 reg-names:124 items:125 - const: llcc0_base126 - const: llcc1_base127 - const: llcc_broadcast_base128 129 - if:130 properties:131 compatible:132 contains:133 enum:134 - qcom,qdu1000-llcc135 - qcom,sc8180x-llcc136 - qcom,sc8280xp-llcc137 - qcom,x1e80100-llcc138 then:139 properties:140 reg:141 items:142 - description: LLCC0 base register region143 - description: LLCC1 base register region144 - description: LLCC2 base register region145 - description: LLCC3 base register region146 - description: LLCC4 base register region147 - description: LLCC5 base register region148 - description: LLCC6 base register region149 - description: LLCC7 base register region150 - description: LLCC broadcast base register region151 reg-names:152 items:153 - const: llcc0_base154 - const: llcc1_base155 - const: llcc2_base156 - const: llcc3_base157 - const: llcc4_base158 - const: llcc5_base159 - const: llcc6_base160 - const: llcc7_base161 - const: llcc_broadcast_base162 163 - if:164 properties:165 compatible:166 contains:167 enum:168 - qcom,sdm845-llcc169 - qcom,sm8150-llcc170 - qcom,sm8250-llcc171 - qcom,sm8350-llcc172 then:173 properties:174 reg:175 items:176 - description: LLCC0 base register region177 - description: LLCC1 base register region178 - description: LLCC2 base register region179 - description: LLCC3 base register region180 - description: LLCC broadcast base register region181 reg-names:182 items:183 - const: llcc0_base184 - const: llcc1_base185 - const: llcc2_base186 - const: llcc3_base187 - const: llcc_broadcast_base188 189 - if:190 properties:191 compatible:192 contains:193 enum:194 - qcom,sm8450-llcc195 - qcom,sm8550-llcc196 - qcom,sm8650-llcc197 then:198 properties:199 reg:200 items:201 - description: LLCC0 base register region202 - description: LLCC1 base register region203 - description: LLCC2 base register region204 - description: LLCC3 base register region205 - description: LLCC broadcast OR register region206 - description: LLCC broadcast AND register region207 reg-names:208 items:209 - const: llcc0_base210 - const: llcc1_base211 - const: llcc2_base212 - const: llcc3_base213 - const: llcc_broadcast_base214 - const: llcc_broadcast_and_base215 216additionalProperties: false217 218examples:219 - |220 #include <dt-bindings/interrupt-controller/arm-gic.h>221 222 soc {223 #address-cells = <2>;224 #size-cells = <2>;225 226 system-cache-controller@1100000 {227 compatible = "qcom,sdm845-llcc";228 reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,229 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,230 <0 0x01300000 0 0x50000>;231 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",232 "llcc3_base", "llcc_broadcast_base";233 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;234 };235 };236