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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright (C) 2020 SiFive, Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: SiFive Composable Cache Controller9 10maintainers:11 - Paul Walmsley <paul.walmsley@sifive.com>12 13description:14 The SiFive Composable Cache Controller is used to provide access to fast copies15 of memory for masters in a Core Complex. The Composable Cache Controller also16 acts as directory-based coherency manager.17 All the properties in ePAPR/DeviceTree specification applies for this platform.18 19select:20 properties:21 compatible:22 contains:23 enum:24 - sifive,ccache025 - sifive,fu540-c000-ccache26 - sifive,fu740-c000-ccache27 28 required:29 - compatible30 31properties:32 compatible:33 oneOf:34 - items:35 - enum:36 - sifive,ccache037 - sifive,fu540-c000-ccache38 - sifive,fu740-c000-ccache39 - const: cache40 - items:41 - enum:42 - starfive,jh7100-ccache43 - starfive,jh7110-ccache44 - const: sifive,ccache045 - const: cache46 - items:47 - const: microchip,mpfs-ccache48 - const: sifive,fu540-c000-ccache49 - const: cache50 51 cache-block-size:52 const: 6453 54 cache-level:55 enum: [2, 3]56 57 cache-sets:58 enum: [1024, 2048]59 60 cache-size:61 const: 209715262 63 cache-unified: true64 65 interrupts:66 minItems: 367 items:68 - description: DirError interrupt69 - description: DataError interrupt70 - description: DataFail interrupt71 - description: DirFail interrupt72 73 reg:74 maxItems: 175 76 next-level-cache: true77 78 memory-region:79 maxItems: 180 description: |81 The reference to the reserved-memory for the L2 Loosely Integrated Memory region.82 The reserved memory node should be defined as per the bindings in reserved-memory.txt.83 84allOf:85 - $ref: /schemas/cache-controller.yaml#86 87 - if:88 properties:89 compatible:90 contains:91 enum:92 - sifive,fu740-c000-ccache93 - starfive,jh7100-ccache94 - starfive,jh7110-ccache95 - microchip,mpfs-ccache96 97 then:98 properties:99 interrupts:100 description: |101 Must contain entries for DirError, DataError, DataFail, DirFail signals.102 minItems: 4103 104 else:105 properties:106 interrupts:107 description: |108 Must contain entries for DirError, DataError and DataFail signals.109 maxItems: 3110 111 - if:112 properties:113 compatible:114 contains:115 enum:116 - sifive,fu740-c000-ccache117 - starfive,jh7100-ccache118 - starfive,jh7110-ccache119 120 then:121 properties:122 cache-sets:123 const: 2048124 125 else:126 properties:127 cache-sets:128 const: 1024129 130 - if:131 properties:132 compatible:133 contains:134 const: sifive,ccache0135 136 then:137 properties:138 cache-level:139 enum: [2, 3]140 141 else:142 properties:143 cache-level:144 const: 2145 146additionalProperties: false147 148required:149 - compatible150 - cache-block-size151 - cache-level152 - cache-sets153 - cache-size154 - cache-unified155 - interrupts156 - reg157 158examples:159 - |160 cache-controller@2010000 {161 compatible = "sifive,fu540-c000-ccache", "cache";162 cache-block-size = <64>;163 cache-level = <2>;164 cache-sets = <1024>;165 cache-size = <2097152>;166 cache-unified;167 reg = <0x2010000 0x1000>;168 interrupt-parent = <&plic0>;169 interrupts = <1>,170 <2>,171 <3>;172 next-level-cache = <&L25>;173 memory-region = <&l2_lim>;174 };175