102 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: UniPhier outer cache controller8 9description: |10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache11 controller system. All of them have a level 2 cache controller, and some12 have a level 3 cache controller as well.13 14maintainers:15 - Masahiro Yamada <yamada.masahiro@socionext.com>16 17properties:18 compatible:19 const: socionext,uniphier-system-cache20 21 reg:22 description: |23 should contain 3 regions: control register, revision register,24 operation register, in this order.25 maxItems: 326 27 interrupts:28 description: |29 Interrupts can be used to notify the completion of cache operations.30 The number of interrupts should match to the number of CPU cores.31 The specified interrupts correspond to CPU0, CPU1, ... in this order.32 minItems: 133 maxItems: 434 35 cache-unified: true36 37 cache-size: true38 39 cache-sets: true40 41 cache-line-size: true42 43 cache-level:44 minimum: 245 maximum: 346 47 next-level-cache: true48 49allOf:50 - $ref: /schemas/cache-controller.yaml#51 52additionalProperties: false53 54required:55 - compatible56 - reg57 - interrupts58 - cache-unified59 - cache-size60 - cache-sets61 - cache-line-size62 - cache-level63 64examples:65 - |66 // System with L2.67 cache-controller@500c0000 {68 compatible = "socionext,uniphier-system-cache";69 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;70 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;71 cache-unified;72 cache-size = <0x140000>;73 cache-sets = <512>;74 cache-line-size = <128>;75 cache-level = <2>;76 };77 - |78 // System with L2 and L3.79 // L2 should specify the next level cache by 'next-level-cache'.80 l2: cache-controller@500c0000 {81 compatible = "socionext,uniphier-system-cache";82 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;83 interrupts = <0 190 4>, <0 191 4>;84 cache-unified;85 cache-size = <0x200000>;86 cache-sets = <512>;87 cache-line-size = <128>;88 cache-level = <2>;89 next-level-cache = <&l3>;90 };91 92 l3: cache-controller@500c8000 {93 compatible = "socionext,uniphier-system-cache";94 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;95 interrupts = <0 174 4>, <0 175 4>;96 cache-unified;97 cache-size = <0x200000>;98 cache-sets = <512>;99 cache-line-size = <256>;100 cache-level = <3>;101 };102