54 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A10 DRAM PLL8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13deprecated: true14 15properties:16 "#clock-cells":17 const: 118 description: >19 The first output is the DRAM clock output, the second is meant20 for peripherals on the SoC.21 22 compatible:23 const: allwinner,sun4i-a10-pll5-clk24 25 reg:26 maxItems: 127 28 clocks:29 maxItems: 130 31 clock-output-names:32 maxItems: 233 34required:35 - "#clock-cells"36 - compatible37 - reg38 - clocks39 - clock-output-names40 41additionalProperties: false42 43examples:44 - |45 clk@1c20020 {46 #clock-cells = <1>;47 compatible = "allwinner,sun4i-a10-pll5-clk";48 reg = <0x01c20020 0x4>;49 clocks = <&osc24M>;50 clock-output-names = "pll5_ddr", "pll5_other";51 };52 53...54