68 lines · yaml
1# SPDX-License-Identifier: GPL-2.0+2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A80 Display Engine Clock Controller8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13properties:14 "#clock-cells":15 const: 116 17 "#reset-cells":18 const: 119 20 compatible:21 const: allwinner,sun9i-a80-de-clks22 23 reg:24 maxItems: 125 26 clocks:27 items:28 - description: Bus Clock29 - description: RAM Bus Clock30 - description: Module Clock31 32 clock-names:33 items:34 - const: mod35 - const: dram36 - const: bus37 38 resets:39 maxItems: 140 41required:42 - "#clock-cells"43 - "#reset-cells"44 - compatible45 - reg46 - clocks47 - clock-names48 - resets49 50additionalProperties: false51 52examples:53 - |54 #include <dt-bindings/clock/sun9i-a80-ccu.h>55 #include <dt-bindings/reset/sun9i-a80-ccu.h>56 57 de_clocks: clock@3000000 {58 compatible = "allwinner,sun9i-a80-de-clks";59 reg = <0x03000000 0x30>;60 clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;61 clock-names = "mod", "dram", "bus";62 resets = <&ccu RST_BUS_DE>;63 #clock-cells = <1>;64 #reset-cells = <1>;65 };66 67...68