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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Amlogic AXG Audio Clock Controller8 9maintainers:10 - Neil Armstrong <neil.armstrong@linaro.org>11 - Jerome Brunet <jbrunet@baylibre.com>12 13description:14 The Amlogic AXG audio clock controller generates and supplies clock to the15 other elements of the audio subsystem, such as fifos, i2s, spdif and pdm16 devices.17 18properties:19 compatible:20 enum:21 - amlogic,axg-audio-clkc22 - amlogic,g12a-audio-clkc23 - amlogic,sm1-audio-clkc24 25 '#clock-cells':26 const: 127 28 '#reset-cells':29 const: 130 31 reg:32 maxItems: 133 34 clocks:35 minItems: 136 items:37 - description: main peripheral bus clock38 - description: input plls to generate clock signals N039 - description: input plls to generate clock signals N140 - description: input plls to generate clock signals N241 - description: input plls to generate clock signals N342 - description: input plls to generate clock signals N443 - description: input plls to generate clock signals N544 - description: input plls to generate clock signals N645 - description: input plls to generate clock signals N746 - description: slave bit clock N0 provided by external components47 - description: slave bit clock N1 provided by external components48 - description: slave bit clock N2 provided by external components49 - description: slave bit clock N3 provided by external components50 - description: slave bit clock N4 provided by external components51 - description: slave bit clock N5 provided by external components52 - description: slave bit clock N6 provided by external components53 - description: slave bit clock N7 provided by external components54 - description: slave bit clock N8 provided by external components55 - description: slave bit clock N9 provided by external components56 - description: slave sample clock N0 provided by external components57 - description: slave sample clock N1 provided by external components58 - description: slave sample clock N2 provided by external components59 - description: slave sample clock N3 provided by external components60 - description: slave sample clock N4 provided by external components61 - description: slave sample clock N5 provided by external components62 - description: slave sample clock N6 provided by external components63 - description: slave sample clock N7 provided by external components64 - description: slave sample clock N8 provided by external components65 - description: slave sample clock N9 provided by external components66 67 clock-names:68 minItems: 169 items:70 - const: pclk71 - const: mst_in072 - const: mst_in173 - const: mst_in274 - const: mst_in375 - const: mst_in476 - const: mst_in577 - const: mst_in678 - const: mst_in779 - const: slv_sclk080 - const: slv_sclk181 - const: slv_sclk282 - const: slv_sclk383 - const: slv_sclk484 - const: slv_sclk585 - const: slv_sclk686 - const: slv_sclk787 - const: slv_sclk888 - const: slv_sclk989 - const: slv_lrclk090 - const: slv_lrclk191 - const: slv_lrclk292 - const: slv_lrclk393 - const: slv_lrclk494 - const: slv_lrclk595 - const: slv_lrclk696 - const: slv_lrclk797 - const: slv_lrclk898 - const: slv_lrclk999 100 resets:101 description: internal reset line102 103required:104 - compatible105 - '#clock-cells'106 - reg107 - clocks108 - clock-names109 - resets110 111allOf:112 - if:113 properties:114 compatible:115 contains:116 enum:117 - amlogic,g12a-audio-clkc118 - amlogic,sm1-audio-clkc119 then:120 required:121 - '#reset-cells'122 else:123 properties:124 '#reset-cells': false125 126additionalProperties: false127 128examples:129 - |130 #include <dt-bindings/clock/axg-clkc.h>131 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>132 apb {133 #address-cells = <2>;134 #size-cells = <2>;135 136 clkc_audio: clock-controller@0 {137 compatible = "amlogic,axg-audio-clkc";138 reg = <0x0 0x0 0x0 0xb4>;139 #clock-cells = <1>;140 141 clocks = <&clkc CLKID_AUDIO>,142 <&clkc CLKID_MPLL0>,143 <&clkc CLKID_MPLL1>,144 <&clkc CLKID_MPLL2>,145 <&clkc CLKID_MPLL3>,146 <&clkc CLKID_HIFI_PLL>,147 <&clkc CLKID_FCLK_DIV3>,148 <&clkc CLKID_FCLK_DIV4>,149 <&clkc CLKID_GP0_PLL>,150 <&slv_sclk0>,151 <&slv_sclk1>,152 <&slv_sclk2>,153 <&slv_sclk3>,154 <&slv_sclk4>,155 <&slv_sclk5>,156 <&slv_sclk6>,157 <&slv_sclk7>,158 <&slv_sclk8>,159 <&slv_sclk9>,160 <&slv_lrclk0>,161 <&slv_lrclk1>,162 <&slv_lrclk2>,163 <&slv_lrclk3>,164 <&slv_lrclk4>,165 <&slv_lrclk5>,166 <&slv_lrclk6>,167 <&slv_lrclk7>,168 <&slv_lrclk8>,169 <&slv_lrclk9>;170 clock-names = "pclk",171 "mst_in0",172 "mst_in1",173 "mst_in2",174 "mst_in3",175 "mst_in4",176 "mst_in5",177 "mst_in6",178 "mst_in7",179 "slv_sclk0",180 "slv_sclk1",181 "slv_sclk2",182 "slv_sclk3",183 "slv_sclk4",184 "slv_sclk5",185 "slv_sclk6",186 "slv_sclk7",187 "slv_sclk8",188 "slv_sclk9",189 "slv_lrclk0",190 "slv_lrclk1",191 "slv_lrclk2",192 "slv_lrclk3",193 "slv_lrclk4",194 "slv_lrclk5",195 "slv_lrclk6",196 "slv_lrclk7",197 "slv_lrclk8",198 "slv_lrclk9";199 resets = <&reset RESET_AUDIO>;200 };201 };202