63 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved3%YAML 1.24---5$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Amlogic C3 series PLL Clock Controller9 10maintainers:11 - Neil Armstrong <neil.armstrong@linaro.org>12 - Jerome Brunet <jbrunet@baylibre.com>13 - Chuan Liu <chuan.liu@amlogic.com>14 - Xianwei Zhao <xianwei.zhao@amlogic.com>15 16properties:17 compatible:18 const: amlogic,c3-pll-clkc19 20 reg:21 maxItems: 122 23 clocks:24 items:25 - description: input top pll26 - description: input mclk pll27 - description: input fix pll28 29 clock-names:30 items:31 - const: top32 - const: mclk33 - const: fix34 35 "#clock-cells":36 const: 137 38required:39 - compatible40 - reg41 - clocks42 - clock-names43 - "#clock-cells"44 45additionalProperties: false46 47examples:48 - |49 apb {50 #address-cells = <2>;51 #size-cells = <2>;52 53 clock-controller@8000 {54 compatible = "amlogic,c3-pll-clkc";55 reg = <0x0 0x8000 0x0 0x1a4>;56 clocks = <&scmi_clk 2>,57 <&scmi_clk 5>,58 <&scmi_clk 12>;59 clock-names = "top", "mclk", "fix";60 #clock-cells = <1>;61 };62 };63