97 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved3%YAML 1.24---5$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Amlogic S4 Peripherals Clock Controller9 10maintainers:11 - Yu Tu <yu.tu@amlogic.com>12 13properties:14 compatible:15 const: amlogic,s4-peripherals-clkc16 17 reg:18 maxItems: 119 20 clocks:21 minItems: 1422 items:23 - description: input fixed pll div224 - description: input fixed pll div2p525 - description: input fixed pll div326 - description: input fixed pll div427 - description: input fixed pll div528 - description: input fixed pll div729 - description: input hifi pll30 - description: input gp0 pll31 - description: input mpll032 - description: input mpll133 - description: input mpll234 - description: input mpll335 - description: input hdmi pll36 - description: input oscillator (usually at 24MHz)37 - description: input external 32kHz reference (optional)38 39 clock-names:40 minItems: 1441 items:42 - const: fclk_div243 - const: fclk_div2p544 - const: fclk_div345 - const: fclk_div446 - const: fclk_div547 - const: fclk_div748 - const: hifi_pll49 - const: gp0_pll50 - const: mpll051 - const: mpll152 - const: mpll253 - const: mpll354 - const: hdmi_pll55 - const: xtal56 - const: ext_32k57 58 "#clock-cells":59 const: 160 61required:62 - compatible63 - reg64 - clocks65 - clock-names66 - "#clock-cells"67 68additionalProperties: false69 70examples:71 - |72 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>73 74 clkc_periphs: clock-controller@fe000000 {75 compatible = "amlogic,s4-peripherals-clkc";76 reg = <0xfe000000 0x49c>;77 clocks = <&clkc_pll 3>,78 <&clkc_pll 13>,79 <&clkc_pll 5>,80 <&clkc_pll 7>,81 <&clkc_pll 9>,82 <&clkc_pll 11>,83 <&clkc_pll 17>,84 <&clkc_pll 15>,85 <&clkc_pll 25>,86 <&clkc_pll 27>,87 <&clkc_pll 29>,88 <&clkc_pll 31>,89 <&clkc_pll 20>,90 <&xtal>;91 clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",92 "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",93 "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";94 #clock-cells = <1>;95 };96...97