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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC3%YAML 1.24---5$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Baikal-T1 Clock Control Unit Dividers9 10maintainers:11 - Serge Semin <fancer.lancer@gmail.com>12 13description: |14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller15 responsible for the chip subsystems clocking and resetting. The CCU is16 connected with an external fixed rate oscillator, which signal is transformed17 into clocks of various frequencies and then propagated to either individual18 IP-blocks or to groups of blocks (clock domains). The transformation is done19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The20 later ones are described in this binding. Each clock domain can be also21 individually reset by using the domain clocks divider configuration22 registers. Baikal-T1 CCU is logically divided into the next components:23 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but24 in general can provide any frequency supported by the CCU PLLs).25 2) PLLs clocks generators (PLLs).26 3) AXI-bus clock dividers (AXI) - described in this binding file.27 4) System devices reference clock dividers (SYS) - described in this binding28 file.29 which are connected with each other as shown on the next figure:30 31 +---------------+32 | Baikal-T1 CCU |33 | +----+------|- MIPS P5600 cores34 | +-|PLLs|------|- DDR controller35 | | +----+ |36 +----+ | | | | |37 |XTAL|--|-+ | | +---+-|38 +----+ | | | +-|AXI|-|- AXI-bus39 | | | +---+-|40 | | | |41 | | +----+---+-|- APB-bus42 | +-------|SYS|-|- Low-speed Devices43 | +---+-|- High-speed Devices44 +---------------+45 46 Each sub-block is represented as a separate DT node and has an individual47 driver to be bound with.48 49 In order to create signals of wide range frequencies the external oscillator50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are51 then passed over CCU dividers to create signals required for the target clock52 domain (like AXI-bus or System Device consumers). The dividers have the53 following structure:54 55 +--------------+56 CLKIN --|->+----+ 1|\ |57 SETCLK--|--|/DIV|->| | |58 CLKDIV--|--| | | |-|->CLKLOUT59 LOCK----|--+----+ | | |60 | |/ |61 | | |62 EN------|-----------+ |63 RST-----|--------------|->RSTOUT64 +--------------+65 66 where CLKIN is the reference clock coming either from CCU PLLs or from an67 external clock oscillator, SETCLK - a command to update the output clock in68 accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of69 the output clock stabilization, EN - enable/disable the divider block,70 RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core71 peculiarities the dividers may lack of some functionality depicted on the72 figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding73 clock provider just doesn't expose either switching functions, or the rate74 configuration, or both of them.75 76 The clock dividers, which output clock is then consumed by the SoC individual77 devices, are united into a single clocks provider called System Devices CCU.78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks79 are called AXI-bus CCU. Both of them use the common clock bindings with no80 custom properties. The list of exported clocks and reset signals can be found81 in the files: 'include/dt-bindings/clock/bt1-ccu.h' and82 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU83 are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed84 to be a children of later one.85 86if:87 properties:88 compatible:89 contains:90 const: baikal,bt1-ccu-axi91 92then:93 properties:94 clocks:95 items:96 - description: CCU SATA PLL output clock97 - description: CCU PCIe PLL output clock98 - description: CCU Ethernet PLL output clock99 100 clock-names:101 items:102 - const: sata_clk103 - const: pcie_clk104 - const: eth_clk105 106else:107 properties:108 clocks:109 items:110 - description: External reference clock111 - description: CCU SATA PLL output clock112 - description: CCU PCIe PLL output clock113 - description: CCU Ethernet PLL output clock114 115 clock-names:116 items:117 - const: ref_clk118 - const: sata_clk119 - const: pcie_clk120 - const: eth_clk121 122properties:123 compatible:124 enum:125 - baikal,bt1-ccu-axi126 - baikal,bt1-ccu-sys127 128 reg:129 maxItems: 1130 131 "#clock-cells":132 const: 1133 134 "#reset-cells":135 const: 1136 137 clocks:138 minItems: 3139 maxItems: 4140 141 clock-names:142 minItems: 3143 maxItems: 4144 145additionalProperties: false146 147required:148 - compatible149 - "#clock-cells"150 - clocks151 - clock-names152 153examples:154 # AXI-bus Clock Control Unit node:155 - |156 #include <dt-bindings/clock/bt1-ccu.h>157 158 clock-controller@1f04d030 {159 compatible = "baikal,bt1-ccu-axi";160 reg = <0x1f04d030 0x030>;161 #clock-cells = <1>;162 #reset-cells = <1>;163 164 clocks = <&ccu_pll CCU_SATA_PLL>,165 <&ccu_pll CCU_PCIE_PLL>,166 <&ccu_pll CCU_ETH_PLL>;167 clock-names = "sata_clk", "pcie_clk", "eth_clk";168 };169 # System Devices Clock Control Unit node:170 - |171 #include <dt-bindings/clock/bt1-ccu.h>172 173 clock-controller@1f04d060 {174 compatible = "baikal,bt1-ccu-sys";175 reg = <0x1f04d060 0x0a0>;176 #clock-cells = <1>;177 #reset-cells = <1>;178 179 clocks = <&clk25m>,180 <&ccu_pll CCU_SATA_PLL>,181 <&ccu_pll CCU_PCIE_PLL>,182 <&ccu_pll CCU_ETH_PLL>;183 clock-names = "ref_clk", "sata_clk", "pcie_clk",184 "eth_clk";185 };186 # Required Clock Control Unit PLL node:187 - |188 ccu_pll: clock-controller@1f04d000 {189 compatible = "baikal,bt1-ccu-pll";190 reg = <0x1f04d000 0x028>;191 #clock-cells = <1>;192 193 clocks = <&clk25m>;194 clock-names = "ref_clk";195 };196...197