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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Broadcom iProc Family Clocks8 9maintainers:10 - Ray Jui <rjui@broadcom.com>11 - Scott Branden <sbranden@broadcom.com>12 13description: |14 The iProc clock controller manages clocks that are common to the iProc family.15 An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL17 comprises of several leaf clocks18 19 ASIU clocks are a special case. These clocks are derived directly from the20 reference clock of the onboard crystal.21 22properties:23 compatible:24 enum:25 - brcm,bcm63138-armpll26 - brcm,cygnus-armpll27 - brcm,cygnus-genpll28 - brcm,cygnus-lcpll029 - brcm,cygnus-mipipll30 - brcm,cygnus-asiu-clk31 - brcm,cygnus-audiopll32 - brcm,hr2-armpll33 - brcm,nsp-armpll34 - brcm,nsp-genpll35 - brcm,nsp-lcpll036 - brcm,ns2-genpll-scr37 - brcm,ns2-genpll-sw38 - brcm,ns2-lcpll-ddr39 - brcm,ns2-lcpll-ports40 - brcm,sr-genpll041 - brcm,sr-genpll142 - brcm,sr-genpll243 - brcm,sr-genpll344 - brcm,sr-genpll445 - brcm,sr-genpll546 - brcm,sr-genpll647 - brcm,sr-lcpll048 - brcm,sr-lcpll149 - brcm,sr-lcpll-pcie50 51 reg:52 minItems: 153 items:54 - description: base register55 - description: power register56 - description: ASIU or split status register57 58 clocks:59 description: The input parent clock phandle for the PLL / ASIU clock. For60 most iProc PLLs, this is an onboard crystal with a fixed rate.61 maxItems: 162 63 '#clock-cells':64 true65 66 clock-output-names:67 minItems: 168 maxItems: 4569 70allOf:71 - if:72 properties:73 compatible:74 contains:75 enum:76 - brcm,cygnus-armpll77 - brcm,nsp-armpll78 then:79 properties:80 '#clock-cells':81 const: 082 else:83 properties:84 '#clock-cells':85 const: 186 required:87 - clock-output-names88 - if:89 properties:90 compatible:91 contains:92 enum:93 - brcm,cygnus-armpll94 - brcm,cygnus-genpll95 - brcm,cygnus-lcpll096 - brcm,cygnus-mipipll97 - brcm,cygnus-asiu-clk98 - brcm,cygnus-audiopll99 then:100 properties:101 clock-output-names:102 description: |103 The following table defines the set of PLL/clock index and ID for Cygnus.104 These clock IDs are defined in:105 "include/dt-bindings/clock/bcm-cygnus.h"106 107 Clock Source (Parent) Index ID108 ----- --------------- ----- --109 crystal N/A N/A N/A110 111 armpll crystal N/A N/A112 113 keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK114 adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK115 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK116 117 genpll crystal 0 BCM_CYGNUS_GENPLL118 axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK119 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK120 ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK121 enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK122 audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK123 can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK124 125 lcpll0 crystal 0 BCM_CYGNUS_LCPLL0126 pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK127 ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK128 sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK129 usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK130 smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK131 ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED132 133 mipipll crystal 0 BCM_CYGNUS_MIPIPLL134 ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED135 ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD136 ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D137 ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED138 ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED139 ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED140 141 audiopll crystal 0 BCM_CYGNUS_AUDIOPLL142 ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0143 ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1144 ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2145 - if:146 properties:147 compatible:148 contains:149 enum:150 - brcm,hr2-armpll151 then:152 properties:153 clock-output-names:154 description: |155 The following table defines the set of PLL/clock for Hurricane 2:156 157 Clock Source Index ID158 ----- ------ ----- --159 crystal N/A N/A N/A160 161 armpll crystal N/A N/A162 - if:163 properties:164 compatible:165 contains:166 enum:167 - brcm,nsp-armpll168 - brcm,nsp-genpll169 - brcm,nsp-lcpll0170 then:171 properties:172 clock-output-names:173 description: |174 The following table defines the set of PLL/clock index and ID for Northstar and175 Northstar Plus. These clock IDs are defined in:176 "include/dt-bindings/clock/bcm-nsp.h"177 178 Clock Source Index ID179 ----- ------ ----- --180 crystal N/A N/A N/A181 182 armpll crystal N/A N/A183 184 genpll crystal 0 BCM_NSP_GENPLL185 phy genpll 1 BCM_NSP_GENPLL_PHY_CLK186 ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK187 usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK188 iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK189 sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK190 sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK191 192 lcpll0 crystal 0 BCM_NSP_LCPLL0193 pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK194 sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK195 ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK196 - if:197 properties:198 compatible:199 contains:200 enum:201 - brcm,ns2-genpll-scr202 - brcm,ns2-genpll-sw203 - brcm,ns2-lcpll-ddr204 - brcm,ns2-lcpll-ports205 then:206 properties:207 clock-output-names:208 description: |209 The following table defines the set of PLL/clock index and ID for Northstar 2.210 These clock IDs are defined in:211 "include/dt-bindings/clock/bcm-ns2.h"212 213 Clock Source Index ID214 ----- ------ ----- --215 crystal N/A N/A N/A216 217 genpll_scr crystal 0 BCM_NS2_GENPLL_SCR218 scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK219 fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK220 audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK221 ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED222 ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED223 ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED224 225 genpll_sw crystal 0 BCM_NS2_GENPLL_SW226 rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK227 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK228 nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK229 chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK230 port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK231 sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK232 233 lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR234 pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK235 ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK236 ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED237 ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED238 ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED239 ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED240 241 lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS242 wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK243 rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK244 ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED245 ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED246 ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED247 ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED248 - if:249 properties:250 compatible:251 contains:252 enum:253 - brcm,sr-genpll0254 - brcm,sr-genpll1255 - brcm,sr-genpll2256 - brcm,sr-genpll3257 - brcm,sr-genpll4258 - brcm,sr-genpll5259 - brcm,sr-genpll6260 - brcm,sr-lcpll0261 - brcm,sr-lcpll1262 - brcm,sr-lcpll-pcie263 then:264 properties:265 clock-output-names:266 description: |267 The following table defines the set of PLL/clock index and ID for Stingray.268 These clock IDs are defined in:269 "include/dt-bindings/clock/bcm-sr.h"270 271 Clock Source Index ID272 ----- ------ ----- --273 crystal N/A N/A N/A274 crmu_ref25m crystal N/A N/A275 276 genpll0 crystal 0 BCM_SR_GENPLL0277 clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK278 clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK279 clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK280 clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK281 clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK282 clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK283 284 genpll1 crystal 0 BCM_SR_GENPLL1285 clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK286 clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK287 288 genpll2 crystal 0 BCM_SR_GENPLL2289 clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK290 clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK291 clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK292 clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK293 clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK294 clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK295 296 genpll3 crystal 0 BCM_SR_GENPLL3297 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK298 clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK299 300 genpll4 crystal 0 BCM_SR_GENPLL4301 clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK302 clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK303 clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK304 clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK305 clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK306 307 genpll5 crystal 0 BCM_SR_GENPLL5308 clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK309 clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK310 clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK311 312 genpll6 crystal 0 BCM_SR_GENPLL6313 clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK314 315 lcpll0 crystal 0 BCM_SR_LCPLL0316 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK317 clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK318 clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK319 clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK320 321 lcpll1 crystal 0 BCM_SR_LCPLL1322 clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK323 clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK324 clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK325 326 lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE327 clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK328 - if:329 properties:330 compatible:331 contains:332 const: brcm,cygnus-genpll333 then:334 properties:335 clock-output-names:336 items:337 - const: genpll338 - const: axi21339 - const: 250mhz340 - const: ihost_sys341 - const: enet_sw342 - const: audio_125343 - const: can344 - if:345 properties:346 compatible:347 contains:348 const: brcm,nsp-lcpll0349 then:350 properties:351 clock-output-names:352 items:353 - const: lcpll0354 - const: pcie_phy355 - const: sdio356 - const: ddr_phy357 - if:358 properties:359 compatible:360 contains:361 const: brcm,nsp-genpll362 then:363 properties:364 clock-output-names:365 items:366 - const: genpll367 - const: phy368 - const: ethernetclk369 - const: usbclk370 - const: iprocfast371 - const: sata1372 - const: sata2373 374required:375 - reg376 - clocks377 - '#clock-cells'378 379additionalProperties: false380 381examples:382 - |383 osc1: oscillator {384 #clock-cells = <0>;385 compatible = "fixed-clock";386 clock-frequency = <25000000>;387 };388 389 genpll@301d000 {390 #clock-cells = <1>;391 compatible = "brcm,cygnus-genpll";392 reg = <0x301d000 0x2c>, <0x301c020 0x4>;393 clocks = <&os1c>;394 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",395 "enet_sw", "audio_125", "can";396 };397 - |398 osc2: oscillator {399 #clock-cells = <0>;400 compatible = "fixed-clock";401 clock-frequency = <25000000>;402 };403 404 asiu_clks@301d048 {405 #clock-cells = <1>;406 compatible = "brcm,cygnus-asiu-clk";407 reg = <0x301d048 0xc>, <0x180aa024 0x4>;408 clocks = <&osc2>;409 clock-output-names = "keypad", "adc/touch", "pwm";410 };411 - |412 arm_clk@0 {413 #clock-cells = <0>;414 compatible = "brcm,nsp-armpll";415 clocks = <&osc>;416 reg = <0x0 0x1000>;417 };418