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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP i.MX8 Audio Clock Mux8 9maintainers:10 - Shengjiu Wang <shengjiu.wang@nxp.com>11 12description: |13 NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP14 used to control Audio related clock on the SoC.15 16properties:17 compatible:18 enum:19 - fsl,imx8dxl-acm20 - fsl,imx8qm-acm21 - fsl,imx8qxp-acm22 23 reg:24 maxItems: 125 26 power-domains:27 minItems: 1328 maxItems: 2129 30 '#clock-cells':31 const: 132 description:33 The clock consumer should specify the desired clock by having the clock34 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h35 for the full list of i.MX8 ACM clock IDs.36 37 clocks:38 minItems: 1339 maxItems: 2740 41 clock-names:42 minItems: 1343 maxItems: 2744 45required:46 - compatible47 - reg48 - power-domains49 - '#clock-cells'50 - clocks51 - clock-names52 53allOf:54 - if:55 properties:56 compatible:57 contains:58 enum:59 - fsl,imx8qxp-acm60 then:61 properties:62 power-domains:63 items:64 - description: power domain of IMX_SC_R_AUDIO_CLK_065 - description: power domain of IMX_SC_R_AUDIO_CLK_166 - description: power domain of IMX_SC_R_MCLK_OUT_067 - description: power domain of IMX_SC_R_MCLK_OUT_168 - description: power domain of IMX_SC_R_AUDIO_PLL_069 - description: power domain of IMX_SC_R_AUDIO_PLL_170 - description: power domain of IMX_SC_R_ASRC_071 - description: power domain of IMX_SC_R_ASRC_172 - description: power domain of IMX_SC_R_ESAI_073 - description: power domain of IMX_SC_R_SAI_074 - description: power domain of IMX_SC_R_SAI_175 - description: power domain of IMX_SC_R_SAI_276 - description: power domain of IMX_SC_R_SAI_377 - description: power domain of IMX_SC_R_SAI_478 - description: power domain of IMX_SC_R_SAI_579 - description: power domain of IMX_SC_R_SPDIF_080 - description: power domain of IMX_SC_R_MQS_081 82 clocks:83 minItems: 1884 maxItems: 1885 86 clock-names:87 items:88 - const: aud_rec_clk0_lpcg_clk89 - const: aud_rec_clk1_lpcg_clk90 - const: aud_pll_div_clk0_lpcg_clk91 - const: aud_pll_div_clk1_lpcg_clk92 - const: ext_aud_mclk093 - const: ext_aud_mclk194 - const: esai0_rx_clk95 - const: esai0_rx_hf_clk96 - const: esai0_tx_clk97 - const: esai0_tx_hf_clk98 - const: spdif0_rx99 - const: sai0_rx_bclk100 - const: sai0_tx_bclk101 - const: sai1_rx_bclk102 - const: sai1_tx_bclk103 - const: sai2_rx_bclk104 - const: sai3_rx_bclk105 - const: sai4_rx_bclk106 107 - if:108 properties:109 compatible:110 contains:111 enum:112 - fsl,imx8qm-acm113 then:114 properties:115 power-domains:116 items:117 - description: power domain of IMX_SC_R_AUDIO_CLK_0118 - description: power domain of IMX_SC_R_AUDIO_CLK_1119 - description: power domain of IMX_SC_R_MCLK_OUT_0120 - description: power domain of IMX_SC_R_MCLK_OUT_1121 - description: power domain of IMX_SC_R_AUDIO_PLL_0122 - description: power domain of IMX_SC_R_AUDIO_PLL_1123 - description: power domain of IMX_SC_R_ASRC_0124 - description: power domain of IMX_SC_R_ASRC_1125 - description: power domain of IMX_SC_R_ESAI_0126 - description: power domain of IMX_SC_R_ESAI_1127 - description: power domain of IMX_SC_R_SAI_0128 - description: power domain of IMX_SC_R_SAI_1129 - description: power domain of IMX_SC_R_SAI_2130 - description: power domain of IMX_SC_R_SAI_3131 - description: power domain of IMX_SC_R_SAI_4132 - description: power domain of IMX_SC_R_SAI_5133 - description: power domain of IMX_SC_R_SAI_6134 - description: power domain of IMX_SC_R_SAI_7135 - description: power domain of IMX_SC_R_SPDIF_0136 - description: power domain of IMX_SC_R_SPDIF_1137 - description: power domain of IMX_SC_R_MQS_0138 139 clocks:140 minItems: 27141 maxItems: 27142 143 clock-names:144 items:145 - const: aud_rec_clk0_lpcg_clk146 - const: aud_rec_clk1_lpcg_clk147 - const: aud_pll_div_clk0_lpcg_clk148 - const: aud_pll_div_clk1_lpcg_clk149 - const: mlb_clk150 - const: hdmi_rx_mclk151 - const: ext_aud_mclk0152 - const: ext_aud_mclk1153 - const: esai0_rx_clk154 - const: esai0_rx_hf_clk155 - const: esai0_tx_clk156 - const: esai0_tx_hf_clk157 - const: esai1_rx_clk158 - const: esai1_rx_hf_clk159 - const: esai1_tx_clk160 - const: esai1_tx_hf_clk161 - const: spdif0_rx162 - const: spdif1_rx163 - const: sai0_rx_bclk164 - const: sai0_tx_bclk165 - const: sai1_rx_bclk166 - const: sai1_tx_bclk167 - const: sai2_rx_bclk168 - const: sai3_rx_bclk169 - const: sai4_rx_bclk170 - const: sai5_tx_bclk171 - const: sai6_rx_bclk172 173 - if:174 properties:175 compatible:176 contains:177 enum:178 - fsl,imx8dxl-acm179 then:180 properties:181 power-domains:182 items:183 - description: power domain of IMX_SC_R_AUDIO_CLK_0184 - description: power domain of IMX_SC_R_AUDIO_CLK_1185 - description: power domain of IMX_SC_R_MCLK_OUT_0186 - description: power domain of IMX_SC_R_MCLK_OUT_1187 - description: power domain of IMX_SC_R_AUDIO_PLL_0188 - description: power domain of IMX_SC_R_AUDIO_PLL_1189 - description: power domain of IMX_SC_R_ASRC_0190 - description: power domain of IMX_SC_R_SAI_0191 - description: power domain of IMX_SC_R_SAI_1192 - description: power domain of IMX_SC_R_SAI_2193 - description: power domain of IMX_SC_R_SAI_3194 - description: power domain of IMX_SC_R_SPDIF_0195 - description: power domain of IMX_SC_R_MQS_0196 197 clocks:198 minItems: 13199 maxItems: 13200 201 clock-names:202 items:203 - const: aud_rec_clk0_lpcg_clk204 - const: aud_rec_clk1_lpcg_clk205 - const: aud_pll_div_clk0_lpcg_clk206 - const: aud_pll_div_clk1_lpcg_clk207 - const: ext_aud_mclk0208 - const: ext_aud_mclk1209 - const: spdif0_rx210 - const: sai0_rx_bclk211 - const: sai0_tx_bclk212 - const: sai1_rx_bclk213 - const: sai1_tx_bclk214 - const: sai2_rx_bclk215 - const: sai3_rx_bclk216 217additionalProperties: false218 219examples:220 # Clock Control Module node:221 - |222 #include <dt-bindings/clock/imx8-lpcg.h>223 #include <dt-bindings/firmware/imx/rsrc.h>224 225 clock-controller@59e00000 {226 compatible = "fsl,imx8qxp-acm";227 reg = <0x59e00000 0x1d0000>;228 #clock-cells = <1>;229 power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,230 <&pd IMX_SC_R_AUDIO_CLK_1>,231 <&pd IMX_SC_R_MCLK_OUT_0>,232 <&pd IMX_SC_R_MCLK_OUT_1>,233 <&pd IMX_SC_R_AUDIO_PLL_0>,234 <&pd IMX_SC_R_AUDIO_PLL_1>,235 <&pd IMX_SC_R_ASRC_0>,236 <&pd IMX_SC_R_ASRC_1>,237 <&pd IMX_SC_R_ESAI_0>,238 <&pd IMX_SC_R_SAI_0>,239 <&pd IMX_SC_R_SAI_1>,240 <&pd IMX_SC_R_SAI_2>,241 <&pd IMX_SC_R_SAI_3>,242 <&pd IMX_SC_R_SAI_4>,243 <&pd IMX_SC_R_SAI_5>,244 <&pd IMX_SC_R_SPDIF_0>,245 <&pd IMX_SC_R_MQS_0>;246 clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,247 <&aud_rec1_lpcg IMX_LPCG_CLK_0>,248 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,249 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,250 <&clk_ext_aud_mclk0>,251 <&clk_ext_aud_mclk1>,252 <&clk_esai0_rx_clk>,253 <&clk_esai0_rx_hf_clk>,254 <&clk_esai0_tx_clk>,255 <&clk_esai0_tx_hf_clk>,256 <&clk_spdif0_rx>,257 <&clk_sai0_rx_bclk>,258 <&clk_sai0_tx_bclk>,259 <&clk_sai1_rx_bclk>,260 <&clk_sai1_tx_bclk>,261 <&clk_sai2_rx_bclk>,262 <&clk_sai3_rx_bclk>,263 <&clk_sai4_rx_bclk>;264 clock-names = "aud_rec_clk0_lpcg_clk",265 "aud_rec_clk1_lpcg_clk",266 "aud_pll_div_clk0_lpcg_clk",267 "aud_pll_div_clk1_lpcg_clk",268 "ext_aud_mclk0",269 "ext_aud_mclk1",270 "esai0_rx_clk",271 "esai0_rx_hf_clk",272 "esai0_tx_clk",273 "esai0_tx_hf_clk",274 "spdif0_rx",275 "sai0_rx_bclk",276 "sai0_tx_bclk",277 "sai1_rx_bclk",278 "sai1_tx_bclk",279 "sai2_rx_bclk",280 "sai3_rx_bclk",281 "sai4_rx_bclk";282 };283