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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock8 9maintainers:10 - Wen He <wen.he_1@nxp.com>11 12description: |13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output14 interface in the display core, as implemented in TSMC CLN28HPM PLL.15 which generate and offers pixel clocks to Display.16 17properties:18 compatible:19 const: fsl,ls1028a-plldig20 21 reg:22 maxItems: 123 24 clocks:25 maxItems: 126 27 '#clock-cells':28 const: 029 30 fsl,vco-hz:31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency32 of this PLL cannot be changed during runtime only at startup. Therefore,33 the output frequencies are very limited and might not even closely match34 the requested frequency. To work around this restriction the user may specify35 its own desired VCO frequency for the PLL.36 minimum: 65000000037 maximum: 130000000038 default: 118800000039 40required:41 - compatible42 - reg43 - clocks44 - '#clock-cells'45 46additionalProperties: false47 48examples:49 # Display PIXEL Clock node:50 - |51 dpclk: clock-display@f1f0000 {52 compatible = "fsl,ls1028a-plldig";53 reg = <0xf1f0000 0xffff>;54 #clock-cells = <0>;55 clocks = <&osc_27m>;56 };57 58...59