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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Clock Block on Freescale QorIQ Platforms8 9maintainers:10 - Frank Li <Frank.Li@nxp.com>11 12description: |13 Freescale QorIQ chips take primary clocking input from the external14 SYSCLK signal. The SYSCLK input (frequency) is multiplied using15 multiple phase locked loops (PLL) to create a variety of frequencies16 which can then be passed to a variety of internal logic, including17 cores and peripheral IP blocks.18 Please refer to the Reference Manual for details.19 20 All references to "1.0" and "2.0" refer to the QorIQ chassis version to21 which the chip complies.22 23 Chassis Version Example Chips24 --------------- -------------25 1.0 p4080, p5020, p504026 2.0 t424027 28 Clock Provider29 30 The clockgen node should act as a clock provider, though in older device31 trees the children of the clockgen node are the clock providers.32 33properties:34 compatible:35 oneOf:36 - items:37 - enum:38 - fsl,p2041-clockgen39 - fsl,p3041-clockgen40 - fsl,p4080-clockgen41 - fsl,p5020-clockgen42 - fsl,p5040-clockgen43 - const: fsl,qoriq-clockgen-1.044 - items:45 - enum:46 - fsl,t1023-clockgen47 - fsl,t1024-clockgen48 - fsl,t1040-clockgen49 - fsl,t1042-clockgen50 - fsl,t2080-clockgen51 - fsl,t2081-clockgen52 - fsl,t4240-clockgen53 - const: fsl,qoriq-clockgen-2.054 - items:55 - enum:56 - fsl,b4420-clockgen57 - fsl,b4860-clockgen58 - const: fsl,b4-clockgen59 - items:60 - enum:61 - fsl,ls1012a-clockgen62 - fsl,ls1021a-clockgen63 - fsl,ls1028a-clockgen64 - fsl,ls1043a-clockgen65 - fsl,ls1046a-clockgen66 - fsl,ls1088a-clockgen67 - fsl,ls2080a-clockgen68 - fsl,lx2160a-clockgen69 70 reg:71 maxItems: 172 73 ranges: true74 75 '#address-cells':76 const: 177 78 '#size-cells':79 const: 180 81 '#clock-cells':82 const: 283 description: |84 The first cell of the clock specifier is the clock type, and the85 second cell is the clock index for the specified type.86 87 Type# Name Index Cell88 0 sysclk must be 089 1 cmux index (n in CLKCnCSR)90 2 hwaccel index (n in CLKCGnHWACSR)91 3 fman 0 for fm1, 1 for fm292 4 platform pll n=pll/(n+1). For example, when n=1,93 that means output_freq=PLL_freq/2.94 5 coreclk must be 095 96 clock-frequency:97 description: Input system clock frequency (SYSCLK)98 99 clocks:100 items:101 - description:102 sysclk may be provided as an input clock. Either clock-frequency103 or clocks must be provided.104 - description:105 A second input clock, called "coreclk", may be provided if106 core PLLs are based on a different input clock from the107 platform PLL.108 minItems: 1109 110 clock-names:111 items:112 - const: sysclk113 - const: coreclk114 115patternProperties:116 '^mux[0-9]@[a-f0-9]+$':117 deprecated: true118 $ref: fsl,qoriq-clock-legacy.yaml119 120 '^sysclk(-[a-z0-9]+)?$':121 deprecated: true122 $ref: fsl,qoriq-clock-legacy.yaml123 124 '^pll[0-9]@[a-f0-9]+$':125 deprecated: true126 $ref: fsl,qoriq-clock-legacy.yaml127 128 '^platform\-pll@[a-f0-9]+$':129 deprecated: true130 $ref: fsl,qoriq-clock-legacy.yaml131 132required:133 - compatible134 - reg135 - '#clock-cells'136 137additionalProperties: false138 139examples:140 - |141 /* clock provider example */142 global-utilities@e1000 {143 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";144 reg = <0xe1000 0x1000>;145 clock-frequency = <133333333>;146 #clock-cells = <2>;147 };148 149 - |150 /* Legacy example */151 global-utilities@e1000 {152 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";153 reg = <0xe1000 0x1000>;154 ranges = <0x0 0xe1000 0x1000>;155 clock-frequency = <133333333>;156 #address-cells = <1>;157 #size-cells = <1>;158 #clock-cells = <2>;159 160 sysclk: sysclk {161 compatible = "fsl,qoriq-sysclk-1.0";162 clock-output-names = "sysclk";163 #clock-cells = <0>;164 };165 166 pll0: pll0@800 {167 compatible = "fsl,qoriq-core-pll-1.0";168 reg = <0x800 0x4>;169 #clock-cells = <1>;170 clocks = <&sysclk>;171 clock-output-names = "pll0", "pll0-div2";172 };173 174 pll1: pll1@820 {175 compatible = "fsl,qoriq-core-pll-1.0";176 reg = <0x820 0x4>;177 #clock-cells = <1>;178 clocks = <&sysclk>;179 clock-output-names = "pll1", "pll1-div2";180 };181 182 mux0: mux0@0 {183 compatible = "fsl,qoriq-core-mux-1.0";184 reg = <0x0 0x4>;185 #clock-cells = <0>;186 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";188 clock-output-names = "cmux0";189 };190 191 mux1: mux1@20 {192 compatible = "fsl,qoriq-core-mux-1.0";193 reg = <0x20 0x4>;194 #clock-cells = <0>;195 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";197 clock-output-names = "cmux1";198 };199 200 platform-pll@c00 {201 #clock-cells = <1>;202 reg = <0xc00 0x4>;203 compatible = "fsl,qoriq-platform-pll-1.0";204 clocks = <&sysclk>;205 clock-output-names = "platform-pll", "platform-pll-div2";206 };207 };208