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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Hisilicon SOC Clock for HI3559AV1008 9maintainers:10 - Dongjiu Geng <gengdongjiu@huawei.com>11 12description: |13 Hisilicon SOC clock control module which supports the clocks, resets and14 power domains on HI3559AV100.15 16 See also:17 dt-bindings/clock/hi3559av100-clock.h18 19properties:20 compatible:21 enum:22 - hisilicon,hi3559av100-clock23 - hisilicon,hi3559av100-shub-clock24 25 reg:26 minItems: 127 maxItems: 228 29 '#clock-cells':30 const: 131 32 '#reset-cells':33 const: 234 description: |35 First cell is reset request register offset.36 Second cell is bit offset in reset request register.37 38required:39 - compatible40 - reg41 - '#clock-cells'42 - '#reset-cells'43 44additionalProperties: false45 46examples:47 - |48 soc {49 #address-cells = <2>;50 #size-cells = <2>;51 52 clock-controller@12010000 {53 compatible = "hisilicon,hi3559av100-clock";54 #clock-cells = <1>;55 #reset-cells = <2>;56 reg = <0x0 0x12010000 0x0 0x10000>;57 };58 };59...60