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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller8 9maintainers:10 - A.s. Dong <aisheng.dong@nxp.com>11 12description: |13 i.MX7ULP Clock functions are under joint control of the System14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)15 modules, and Core Mode Controller (CMC)1 blocks16 17 The clocking scheme provides clear separation between M4 domain18 and A7 domain. Except for a few clock sources shared between two19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),20 and and the Fast IRC clock (FIRCLK), clock sources and clock21 management are separated and contained within each domain.22 23 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.25 26 Note: this binding doc is only for A7 clock domain.27 28 The System Clock Generation (SCG) is responsible for clock generation29 and distribution across this device. Functions performed by the SCG30 include: clock reference selection, generation of clock used to derive31 processor, system, peripheral bus and external memory interface clocks,32 source selection for peripheral clocks and control of power saving33 clock gating mode.34 35 The clock consumer should specify the desired clock by having the clock36 ID in its "clocks" phandle cell.37 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of38 i.MX7ULP clock IDs of each module.39 40properties:41 compatible:42 const: fsl,imx7ulp-scg143 44 reg:45 maxItems: 146 47 '#clock-cells':48 const: 149 50 clocks:51 items:52 - description: rtc osc53 - description: system osc54 - description: slow internal reference clock55 - description: fast internal reference clock56 - description: usb PLL57 58 clock-names:59 items:60 - const: rosc61 - const: sosc62 - const: sirc63 - const: firc64 - const: upll65 66required:67 - compatible68 - reg69 - '#clock-cells'70 - clocks71 - clock-names72 73additionalProperties: false74 75examples:76 - |77 #include <dt-bindings/clock/imx7ulp-clock.h>78 #include <dt-bindings/interrupt-controller/arm-gic.h>79 80 clock-controller@403e0000 {81 compatible = "fsl,imx7ulp-scg1";82 reg = <0x403e0000 0x10000>;83 clocks = <&rosc>, <&sosc>, <&sirc>,84 <&firc>, <&upll>;85 clock-names = "rosc", "sosc", "sirc",86 "firc", "upll";87 #clock-cells = <1>;88 };89