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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP i.MX8MP AudioMIX Block Control8 9maintainers:10 - Marek Vasut <marex@denx.de>11 12description: |13 NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP14 used to control Audio related clock on the SoC.15 16properties:17 compatible:18 const: fsl,imx8mp-audio-blk-ctrl19 20 reg:21 maxItems: 122 23 power-domains:24 maxItems: 125 26 clocks:27 minItems: 728 maxItems: 729 30 clock-names:31 items:32 - const: ahb33 - const: sai134 - const: sai235 - const: sai336 - const: sai537 - const: sai638 - const: sai739 40 '#clock-cells':41 const: 142 description:43 The clock consumer should specify the desired clock by having the clock44 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h45 for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.46 47 '#reset-cells':48 const: 149 50required:51 - compatible52 - reg53 - clocks54 - clock-names55 - power-domains56 - '#clock-cells'57 58additionalProperties: false59 60examples:61 # Clock Control Module node:62 - |63 #include <dt-bindings/clock/imx8mp-clock.h>64 65 clock-controller@30e20000 {66 compatible = "fsl,imx8mp-audio-blk-ctrl";67 reg = <0x30e20000 0x10000>;68 #clock-cells = <1>;69 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,70 <&clk IMX8MP_CLK_SAI1>,71 <&clk IMX8MP_CLK_SAI2>,72 <&clk IMX8MP_CLK_SAI3>,73 <&clk IMX8MP_CLK_SAI5>,74 <&clk IMX8MP_CLK_SAI6>,75 <&clk IMX8MP_CLK_SAI7>;76 clock-names = "ahb",77 "sai1", "sai2", "sai3",78 "sai5", "sai6", "sai7";79 power-domains = <&pgc_audio>;80 };81 82...83