51 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module8 9maintainers:10 - Jacky Bai <ping.bai@nxp.com>11 12description: |13 On i.MX8ULP, The clock sources generation, distribution and management is14 under the control of several CGCs & PCCs modules. The PCC modules control15 software reset, clock selection, optional division and clock gating mode16 for peripherals.17 18properties:19 compatible:20 enum:21 - fsl,imx8ulp-pcc322 - fsl,imx8ulp-pcc423 - fsl,imx8ulp-pcc524 25 reg:26 maxItems: 127 28 '#clock-cells':29 const: 130 31 '#reset-cells':32 const: 133 34required:35 - compatible36 - reg37 - '#clock-cells'38 - '#reset-cells'39 40additionalProperties: false41 42examples:43 # Peripheral Clock Control Module node:44 - |45 clock-controller@292d0000 {46 compatible = "fsl,imx8ulp-pcc3";47 reg = <0x292d0000 0x10000>;48 #clock-cells = <1>;49 #reset-cells = <1>;50 };51