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1Binding for keystone PLLs. The main PLL IP typically has a multiplier,2a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL3and PAPLL are controlled by the memory mapped register where as the Main4PLL is controlled by a PLL controller registers along with memory mapped5registers.6 7This binding uses the common clock binding[1].8 9[1] Documentation/devicetree/bindings/clock/clock-bindings.txt10 11Required properties:12- #clock-cells : from common clock binding; shall be set to 0.13- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"14- clocks : parent clock phandle15- reg - pll control0 and pll multiplier registers16- reg-names : control, multiplier and post-divider. The multiplier and17 post-divider registers are applicable only for main pll clock18- fixed-postdiv : fixed post divider value. If absent, use clkod register bits19 for postdiv20 21Example:22 mainpllclk: mainpllclk@2310110 {23 #clock-cells = <0>;24 compatible = "ti,keystone,main-pll-clock";25 clocks = <&refclksys>;26 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;27 reg-names = "control", "multiplier", "post-divider";28 fixed-postdiv = <2>;29 };30 31 papllclk: papllclk@2620358 {32 #clock-cells = <0>;33 compatible = "ti,keystone,pll-clock";34 clocks = <&refclkpass>;35 clock-output-names = "pa-pll-clk";36 reg = <0x02620358 4>;37 reg-names = "control";38 };39 40Required properties:41- #clock-cells : from common clock binding; shall be set to 0.42- compatible : shall be "ti,keystone,pll-mux-clock"43- clocks : link phandles of parent clocks44- reg - pll mux register45- bit-shift : number of bits to shift the bit-mask46- bit-mask : arbitrary bitmask for programming the mux47 48Optional properties:49- clock-output-names : From common clock binding.50 51Example:52 mainmuxclk: mainmuxclk@2310108 {53 #clock-cells = <0>;54 compatible = "ti,keystone,pll-mux-clock";55 clocks = <&mainpllclk>, <&refclkmain>;56 reg = <0x02310108 4>;57 bit-shift = <23>;58 bit-mask = <1>;59 clock-output-names = "mainmuxclk";60 };61 62Required properties:63- #clock-cells : from common clock binding; shall be set to 0.64- compatible : shall be "ti,keystone,pll-divider-clock"65- clocks : parent clock phandle66- reg - pll mux register67- bit-shift : number of bits to shift the bit-mask68- bit-mask : arbitrary bitmask for programming the divider69 70Optional properties:71- clock-output-names : From common clock binding.72 73Example:74 gemtraceclk: gemtraceclk@2310120 {75 #clock-cells = <0>;76 compatible = "ti,keystone,pll-divider-clock";77 clocks = <&mainmuxclk>;78 reg = <0x02310120 4>;79 bit-shift = <0>;80 bit-mask = <8>;81 clock-output-names = "gemtraceclk";82 };83