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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Infrastructure System Configuration Controller8 9maintainers:10 - Matthias Brugger <matthias.bgg@gmail.com>11 12description:13 The Mediatek infracfg controller provides various clocks and reset outputs14 to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,15 and reset values in <dt-bindings/reset/mt*-reset.h> and16 <dt-bindings/reset/mt*-resets.h>.17 18properties:19 compatible:20 oneOf:21 - items:22 - enum:23 - mediatek,mt2701-infracfg24 - mediatek,mt2712-infracfg25 - mediatek,mt6765-infracfg26 - mediatek,mt6795-infracfg27 - mediatek,mt6779-infracfg_ao28 - mediatek,mt6797-infracfg29 - mediatek,mt7622-infracfg30 - mediatek,mt7629-infracfg31 - mediatek,mt7981-infracfg32 - mediatek,mt7986-infracfg33 - mediatek,mt7988-infracfg34 - mediatek,mt8135-infracfg35 - mediatek,mt8167-infracfg36 - mediatek,mt8173-infracfg37 - mediatek,mt8183-infracfg38 - mediatek,mt8516-infracfg39 - const: syscon40 - items:41 - const: mediatek,mt7623-infracfg42 - const: mediatek,mt2701-infracfg43 - const: syscon44 45 reg:46 maxItems: 147 48 '#clock-cells':49 const: 150 51 '#reset-cells':52 const: 153 54required:55 - compatible56 - reg57 - '#clock-cells'58 59if:60 properties:61 compatible:62 contains:63 enum:64 - mediatek,mt2701-infracfg65 - mediatek,mt2712-infracfg66 - mediatek,mt6795-infracfg67 - mediatek,mt7622-infracfg68 - mediatek,mt7986-infracfg69 - mediatek,mt8135-infracfg70 - mediatek,mt8173-infracfg71 - mediatek,mt8183-infracfg72then:73 required:74 - '#reset-cells'75 76additionalProperties: false77 78examples:79 - |80 infracfg: clock-controller@10001000 {81 compatible = "mediatek,mt8173-infracfg", "syscon";82 reg = <0x10001000 0x1000>;83 #clock-cells = <1>;84 #reset-cells = <1>;85 };86