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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Functional Clock Controller for MT67958 9maintainers:10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>11 - Chun-Jie Chen <chun-jie.chen@mediatek.com>12 13description: |14 The clock architecture in MediaTek like below15 PLLs -->16 dividers -->17 muxes18 -->19 clock gate20 21 The devices provide clock gate control in different IP blocks.22 23properties:24 compatible:25 enum:26 - mediatek,mt6795-mfgcfg27 - mediatek,mt6795-vdecsys28 - mediatek,mt6795-vencsys29 30 reg:31 maxItems: 132 33 '#clock-cells':34 const: 135 36required:37 - compatible38 - reg39 - '#clock-cells'40 41additionalProperties: false42 43examples:44 - |45 soc {46 #address-cells = <2>;47 #size-cells = <2>;48 49 mfgcfg: clock-controller@13000000 {50 compatible = "mediatek,mt6795-mfgcfg";51 reg = <0 0x13000000 0 0x1000>;52 #clock-cells = <1>;53 };54 55 vdecsys: clock-controller@16000000 {56 compatible = "mediatek,mt6795-vdecsys";57 reg = <0 0x16000000 0 0x1000>;58 #clock-cells = <1>;59 };60 61 vencsys: clock-controller@18000000 {62 compatible = "mediatek,mt6795-vencsys";63 reg = <0 0x18000000 0 0x1000>;64 #clock-cells = <1>;65 };66 };67