48 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek PCIESYS clock and reset controller8 9description:10 The MediaTek PCIESYS controller provides various clocks to the system.11 12maintainers:13 - Matthias Brugger <matthias.bgg@gmail.com>14 15properties:16 compatible:17 oneOf:18 - items:19 - const: mediatek,mt7622-pciesys20 - const: syscon21 - const: mediatek,mt7629-pciesys22 23 reg:24 maxItems: 125 26 "#clock-cells":27 const: 128 description: The available clocks are defined in dt-bindings/clock/mt*-clk.h29 30 "#reset-cells":31 const: 132 33required:34 - reg35 - "#clock-cells"36 - "#reset-cells"37 38additionalProperties: false39 40examples:41 - |42 clock-controller@1a100800 {43 compatible = "mediatek,mt7622-pciesys", "syscon";44 reg = <0x1a100800 0x1000>;45 #clock-cells = <1>;46 #reset-cells = <1>;47 };48