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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Functional Clock Controller for MT81868 9maintainers:10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>11 12description: |13 The clock architecture in MediaTek like below14 PLLs -->15 dividers -->16 muxes17 -->18 clock gate19 20 The devices provide clock gate control in different IP blocks.21 22properties:23 compatible:24 items:25 - enum:26 - mediatek,mt8186-imp_iic_wrap27 - mediatek,mt8186-mfgsys28 - mediatek,mt8186-wpesys29 - mediatek,mt8186-imgsys130 - mediatek,mt8186-imgsys231 - mediatek,mt8186-vdecsys32 - mediatek,mt8186-vencsys33 - mediatek,mt8186-camsys34 - mediatek,mt8186-camsys_rawa35 - mediatek,mt8186-camsys_rawb36 - mediatek,mt8186-mdpsys37 - mediatek,mt8186-ipesys38 reg:39 maxItems: 140 41 '#clock-cells':42 const: 143 44required:45 - compatible46 - reg47 48additionalProperties: false49 50examples:51 - |52 imp_iic_wrap: clock-controller@11017000 {53 compatible = "mediatek,mt8186-imp_iic_wrap";54 reg = <0x11017000 0x1000>;55 #clock-cells = <1>;56 };57