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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek System Clock Controller for MT81868 9maintainers:10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>11 12description: |13 The clock architecture in MediaTek like below14 PLLs -->15 dividers -->16 muxes17 -->18 clock gate19 20 The apmixedsys provides most of PLLs which generated from SoC 26m.21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.23 The mcusys provides mux control to select the clock source in AP MCU.24 The device nodes also provide the system control capacity for configuration.25 26properties:27 compatible:28 items:29 - enum:30 - mediatek,mt8186-mcusys31 - mediatek,mt8186-topckgen32 - mediatek,mt8186-infracfg_ao33 - mediatek,mt8186-apmixedsys34 - const: syscon35 36 reg:37 maxItems: 138 39 '#clock-cells':40 const: 141 42 '#reset-cells':43 const: 144 45required:46 - compatible47 - reg48 49additionalProperties: false50 51examples:52 - |53 topckgen: syscon@10000000 {54 compatible = "mediatek,mt8186-topckgen", "syscon";55 reg = <0x10000000 0x1000>;56 #clock-cells = <1>;57 };58