70 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Functional Clock Controller for MT81888 9maintainers:10 - Garmin Chang <garmin.chang@mediatek.com>11 12description: |13 The clock architecture in MediaTek like below14 PLLs -->15 dividers -->16 muxes17 -->18 clock gate19 20 The devices provide clock gate control in different IP blocks.21 22properties:23 compatible:24 enum:25 - mediatek,mt8188-adsp-audio26m26 - mediatek,mt8188-camsys27 - mediatek,mt8188-camsys-rawa28 - mediatek,mt8188-camsys-rawb29 - mediatek,mt8188-camsys-yuva30 - mediatek,mt8188-camsys-yuvb31 - mediatek,mt8188-ccusys32 - mediatek,mt8188-imgsys33 - mediatek,mt8188-imgsys-wpe134 - mediatek,mt8188-imgsys-wpe235 - mediatek,mt8188-imgsys-wpe336 - mediatek,mt8188-imgsys1-dip-nr37 - mediatek,mt8188-imgsys1-dip-top38 - mediatek,mt8188-imp-iic-wrap-c39 - mediatek,mt8188-imp-iic-wrap-en40 - mediatek,mt8188-imp-iic-wrap-w41 - mediatek,mt8188-ipesys42 - mediatek,mt8188-mfgcfg43 - mediatek,mt8188-vdecsys44 - mediatek,mt8188-vdecsys-soc45 - mediatek,mt8188-vencsys46 - mediatek,mt8188-wpesys47 - mediatek,mt8188-wpesys-vpp048 49 reg:50 maxItems: 151 52 '#clock-cells':53 const: 154 55required:56 - compatible57 - reg58 - '#clock-cells'59 60additionalProperties: false61 62examples:63 - |64 clock-controller@11283000 {65 compatible = "mediatek,mt8188-imp-iic-wrap-c";66 reg = <0x11283000 0x1000>;67 #clock-cells = <1>;68 };69 70