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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek System Clock Controller for MT81928 9maintainers:10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>11 12description:13 The Mediatek system clock controller provides various clocks and system configuration14 like reset and bus protection on MT8192.15 16properties:17 compatible:18 items:19 - enum:20 - mediatek,mt8192-topckgen21 - mediatek,mt8192-infracfg22 - mediatek,mt8192-pericfg23 - mediatek,mt8192-apmixedsys24 - const: syscon25 26 reg:27 maxItems: 128 29 '#clock-cells':30 const: 131 32 '#reset-cells':33 const: 134 35required:36 - compatible37 - reg38 39additionalProperties: false40 41examples:42 - |43 topckgen: syscon@10000000 {44 compatible = "mediatek,mt8192-topckgen", "syscon";45 reg = <0x10000000 0x1000>;46 #clock-cells = <1>;47 };48 49 - |50 infracfg: syscon@10001000 {51 compatible = "mediatek,mt8192-infracfg", "syscon";52 reg = <0x10001000 0x1000>;53 #clock-cells = <1>;54 };55 56 - |57 pericfg: syscon@10003000 {58 compatible = "mediatek,mt8192-pericfg", "syscon";59 reg = <0x10003000 0x1000>;60 #clock-cells = <1>;61 };62 63 - |64 apmixedsys: syscon@1000c000 {65 compatible = "mediatek,mt8192-apmixedsys", "syscon";66 reg = <0x1000c000 0x1000>;67 #clock-cells = <1>;68 };69