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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek System Clock Controller for MT83658 9maintainers:10 - Markus Schneider-Pargmann <msp@baylibre.com>11 12description:13 The apmixedsys module provides most of PLLs which generated from SoC 26m.14 The topckgen provides dividers and muxes which provides the clock source to other IP blocks.15 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.16 17properties:18 compatible:19 items:20 - enum:21 - mediatek,mt8365-topckgen22 - mediatek,mt8365-infracfg23 - mediatek,mt8365-apmixedsys24 - mediatek,mt8365-pericfg25 - mediatek,mt8365-mcucfg26 - const: syscon27 28 reg:29 maxItems: 130 31 '#clock-cells':32 const: 133 34required:35 - compatible36 - reg37 - '#clock-cells'38 39additionalProperties: false40 41examples:42 - |43 topckgen: clock-controller@10000000 {44 compatible = "mediatek,mt8365-topckgen", "syscon";45 reg = <0x10000000 0x1000>;46 #clock-cells = <1>;47 };48