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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MTMIPS SoCs System Controller8 9maintainers:10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>11 12description: |13 MediaTek MIPS and Ralink SoCs provides a system controller to allow14 to access to system control registers. These registers include clock15 and reset related ones so this node is both clock and reset provider16 for the rest of the world.17 18 These SoCs have an XTAL from where the cpu clock is19 provided as well as derived clocks for the bus and the peripherals.20 21properties:22 compatible:23 items:24 - enum:25 - ralink,mt7620-sysc26 - ralink,mt7628-sysc27 - ralink,mt7688-sysc28 - ralink,rt2880-sysc29 - ralink,rt3050-sysc30 - ralink,rt3052-sysc31 - ralink,rt3352-sysc32 - ralink,rt3883-sysc33 - ralink,rt5350-sysc34 - const: syscon35 36 reg:37 maxItems: 138 39 '#clock-cells':40 description:41 The first cell indicates the clock number.42 const: 143 44 '#reset-cells':45 description:46 The first cell indicates the reset bit within the register.47 const: 148 49required:50 - compatible51 - reg52 - '#clock-cells'53 - '#reset-cells'54 55additionalProperties: false56 57examples:58 - |59 syscon@0 {60 compatible = "ralink,rt5350-sysc", "syscon";61 reg = <0x0 0x100>;62 #clock-cells = <1>;63 #reset-cells = <1>;64 };65