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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microchip LAN966X Generic Clock Controller8 9maintainers:10 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>11 12description: |13 The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,14 ddr_clk and sys_clk. This clock controller generates and supplies15 clock to various peripherals within the SoC.16 17properties:18 compatible:19 const: microchip,lan966x-gck20 21 reg:22 minItems: 123 items:24 - description: Generic clock registers25 - description: Optional gate clock registers26 27 clocks:28 items:29 - description: CPU clock source30 - description: DDR clock source31 - description: System clock source32 33 clock-names:34 items:35 - const: cpu36 - const: ddr37 - const: sys38 39 '#clock-cells':40 const: 141 42required:43 - compatible44 - reg45 - clocks46 - clock-names47 - '#clock-cells'48 49additionalProperties: false50 51examples:52 - |53 clks: clock-controller@e00c00a8 {54 compatible = "microchip,lan966x-gck";55 #clock-cells = <1>;56 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;57 clock-names = "cpu", "ddr", "sys";58 reg = <0xe00c00a8 0x38>;59 };60...61