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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry8 9maintainers:10 - Conor Dooley <conor.dooley@microchip.com>11 12description: |13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of14 these blocks contains two PLLs and 2 DLLs & are located in the four corners of15 the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html17 18properties:19 compatible:20 const: microchip,mpfs-ccc21 22 reg:23 items:24 - description: PLL0's control registers25 - description: PLL1's control registers26 - description: DLL0's control registers27 - description: DLL1's control registers28 29 clocks:30 description:31 The CCC PLL's have two input clocks. It is required that even if the input32 clocks are identical that both are provided.33 minItems: 234 items:35 - description: PLL0's refclk036 - description: PLL0's refclk137 - description: PLL1's refclk038 - description: PLL1's refclk139 - description: DLL0's refclk40 - description: DLL1's refclk41 42 clock-names:43 minItems: 244 items:45 - const: pll0_ref046 - const: pll0_ref147 - const: pll1_ref048 - const: pll1_ref149 - const: dll0_ref50 - const: dll1_ref51 52 '#clock-cells':53 const: 154 description: |55 The clock consumer should specify the desired clock by having the clock56 ID in its "clocks" phandle cell.57 See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of58 PolarFire clock IDs.59 60required:61 - compatible62 - reg63 - clocks64 - clock-names65 - '#clock-cells'66 67additionalProperties: false68 69examples:70 - |71 clock-controller@38100000 {72 compatible = "microchip,mpfs-ccc";73 reg = <0x38010000 0x1000>, <0x38020000 0x1000>,74 <0x39010000 0x1000>, <0x39020000 0x1000>;75 #clock-cells = <1>;76 clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,77 <&refclk_ccc>, <&refclk_ccc>;78 clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",79 "dll0_ref", "dll1_ref";80 };81