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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Nuvoton MA35D1 Clock Controller Module8 9maintainers:10 - Chi-Fang Li <cfli0@nuvoton.com>11 - Jacky Huang <ychuang3@nuvoton.com>12 13description: |14 The MA35D1 clock controller generates clocks for the whole chip,15 including system clocks and all peripheral clocks.16 17 See also:18 include/dt-bindings/clock/ma35d1-clk.h19 20properties:21 compatible:22 items:23 - const: nuvoton,ma35d1-clk24 25 reg:26 maxItems: 127 28 "#clock-cells":29 const: 130 31 clocks:32 maxItems: 133 34 nuvoton,pll-mode:35 description:36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,37 EPLL, and VPLL in sequential.38 maxItems: 539 items:40 enum:41 - integer42 - fractional43 - spread-spectrum44 $ref: /schemas/types.yaml#/definitions/non-unique-string-array45 46required:47 - compatible48 - reg49 - "#clock-cells"50 - clocks51 52additionalProperties: false53 54examples:55 - |56 57 clock-controller@40460200 {58 compatible = "nuvoton,ma35d1-clk";59 reg = <0x40460200 0x100>;60 #clock-cells = <1>;61 clocks = <&clk_hxt>;62 };63...64