111 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra Clock and Reset Controller8 9maintainers:10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>12 13description: |14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.16 17 CLKGEN provides the registers to program the PLLs. It controls most of18 the clock source programming and most of the clock dividers.19 20 CLKGEN input signals include the external clock for the reference frequency21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).22 23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.24 25 RSTGEN provides the registers needed to control resetting of each block in26 the Tegra system.27 28properties:29 compatible:30 enum:31 - nvidia,tegra124-car32 - nvidia,tegra132-car33 34 reg:35 maxItems: 136 37 '#clock-cells':38 const: 139 40 "#reset-cells":41 const: 142 43 nvidia,external-memory-controller:44 $ref: /schemas/types.yaml#/definitions/phandle45 description:46 phandle of the external memory controller node47 48patternProperties:49 "^emc-timings-[0-9]+$":50 type: object51 properties:52 nvidia,ram-code:53 $ref: /schemas/types.yaml#/definitions/uint3254 description:55 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that56 this timing set is used for57 58 patternProperties:59 "^timing-[0-9]+$":60 type: object61 properties:62 clock-frequency:63 description:64 external memory clock rate in Hz65 minimum: 100000066 maximum: 100000000067 68 nvidia,parent-clock-frequency:69 $ref: /schemas/types.yaml#/definitions/uint3270 description:71 rate of parent clock in Hz72 minimum: 100000073 maximum: 100000000074 75 clocks:76 items:77 - description: parent clock of EMC78 79 clock-names:80 items:81 - const: emc-parent82 83 required:84 - clock-frequency85 - nvidia,parent-clock-frequency86 - clocks87 - clock-names88 89 additionalProperties: false90 91 additionalProperties: false92 93required:94 - compatible95 - reg96 - '#clock-cells'97 - "#reset-cells"98 99additionalProperties: false100 101examples:102 - |103 #include <dt-bindings/clock/tegra124-car.h>104 105 car: clock-controller@60006000 {106 compatible = "nvidia,tegra124-car";107 reg = <0x60006000 0x1000>;108 #clock-cells = <1>;109 #reset-cells = <1>;110 };111