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1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra Clock and Reset Controller8 9maintainers:10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>12 13description: |14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.16 17 CLKGEN provides the registers to program the PLLs. It controls most of18 the clock source programming and most of the clock dividers.19 20 CLKGEN input signals include the external clock for the reference frequency21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).22 23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.24 25 RSTGEN provides the registers needed to control resetting of each block in26 the Tegra system.27 28properties:29 compatible:30 enum:31 - nvidia,tegra20-car32 - nvidia,tegra30-car33 - nvidia,tegra114-car34 - nvidia,tegra210-car35 36 reg:37 maxItems: 138 39 '#clock-cells':40 const: 141 42 "#reset-cells":43 const: 144 45patternProperties:46 "^(sclk)|(pll-[cem])$":47 type: object48 properties:49 compatible:50 enum:51 - nvidia,tegra20-sclk52 - nvidia,tegra30-sclk53 - nvidia,tegra30-pllc54 - nvidia,tegra30-plle55 - nvidia,tegra30-pllm56 57 operating-points-v2: true58 59 clocks:60 items:61 - description: node's clock62 63 power-domains:64 maxItems: 165 description: phandle to the core SoC power domain66 67 required:68 - compatible69 - operating-points-v270 - clocks71 - power-domains72 73 additionalProperties: false74 75required:76 - compatible77 - reg78 - '#clock-cells'79 - "#reset-cells"80 81additionalProperties: false82 83examples:84 - |85 #include <dt-bindings/clock/tegra20-car.h>86 87 car: clock-controller@60006000 {88 compatible = "nvidia,tegra20-car";89 reg = <0x60006000 0x1000>;90 #clock-cells = <1>;91 #reset-cells = <1>;92 93 sclk {94 compatible = "nvidia,tegra20-sclk";95 operating-points-v2 = <&opp_table>;96 clocks = <&tegra_car TEGRA20_CLK_SCLK>;97 power-domains = <&domain>;98 };99 };100