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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock Controller on SM61258 9maintainers:10 - Martin Botka <martin.botka@somainline.org>11 12description: |13 Qualcomm display clock control module provides the clocks and power domains14 on SM6125.15 16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h17 18properties:19 compatible:20 enum:21 - qcom,sm6125-dispcc22 23 clocks:24 items:25 - description: Board XO source26 - description: Byte clock from DSI PHY027 - description: Pixel clock from DSI PHY028 - description: Pixel clock from DSI PHY129 - description: Link clock from DP PHY30 - description: VCO DIV clock from DP PHY31 - description: AHB config clock from GCC32 - description: GPLL0 div source from GCC33 34 clock-names:35 items:36 - const: bi_tcxo37 - const: dsi0_phy_pll_out_byteclk38 - const: dsi0_phy_pll_out_dsiclk39 - const: dsi1_phy_pll_out_dsiclk40 - const: dp_phy_pll_link_clk41 - const: dp_phy_pll_vco_div_clk42 - const: cfg_ahb_clk43 - const: gcc_disp_gpll0_div_clk_src44 45 '#clock-cells':46 const: 147 48 '#power-domain-cells':49 const: 150 51 power-domains:52 description:53 A phandle and PM domain specifier for the CX power domain.54 maxItems: 155 56 required-opps:57 description:58 A phandle to an OPP node describing the power domain's performance point.59 maxItems: 160 61 reg:62 maxItems: 163 64required:65 - compatible66 - reg67 - clocks68 - clock-names69 - '#clock-cells'70 - '#power-domain-cells'71 72additionalProperties: false73 74examples:75 - |76 #include <dt-bindings/clock/qcom,rpmcc.h>77 #include <dt-bindings/clock/qcom,gcc-sm6125.h>78 #include <dt-bindings/power/qcom-rpmpd.h>79 clock-controller@5f00000 {80 compatible = "qcom,sm6125-dispcc";81 reg = <0x5f00000 0x20000>;82 83 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,84 <&dsi0_phy 0>,85 <&dsi0_phy 1>,86 <&dsi1_phy 1>,87 <&dp_phy 0>,88 <&dp_phy 1>,89 <&gcc GCC_DISP_AHB_CLK>,90 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;91 clock-names = "bi_tcxo",92 "dsi0_phy_pll_out_byteclk",93 "dsi0_phy_pll_out_dsiclk",94 "dsi1_phy_pll_out_dsiclk",95 "dp_phy_pll_link_clk",96 "dp_phy_pll_vco_div_clk",97 "cfg_ahb_clk",98 "gcc_disp_gpll0_div_clk_src";99 100 required-opps = <&rpmhpd_opp_ret>;101 power-domains = <&rpmpd SM6125_VDDCX>;102 103 #clock-cells = <1>;104 #power-domain-cells = <1>;105 };106...107