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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Display Clock & Reset Controller on SM63508 9maintainers:10 - Konrad Dybcio <konradybcio@kernel.org>11 12description: |13 Qualcomm display clock control module provides the clocks, resets and power14 domains on SM6350.15 16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h17 18properties:19 compatible:20 const: qcom,sm6350-dispcc21 22 clocks:23 items:24 - description: Board XO source25 - description: GPLL0 source from GCC26 - description: Byte clock from DSI PHY27 - description: Pixel clock from DSI PHY28 - description: Link clock from DP PHY29 - description: VCO DIV clock from DP PHY30 31 clock-names:32 items:33 - const: bi_tcxo34 - const: gcc_disp_gpll0_clk35 - const: dsi0_phy_pll_out_byteclk36 - const: dsi0_phy_pll_out_dsiclk37 - const: dp_phy_pll_link_clk38 - const: dp_phy_pll_vco_div_clk39 40required:41 - compatible42 - clocks43 - clock-names44 - '#power-domain-cells'45 46allOf:47 - $ref: qcom,gcc.yaml#48 49unevaluatedProperties: false50 51examples:52 - |53 #include <dt-bindings/clock/qcom,gcc-sm6350.h>54 #include <dt-bindings/clock/qcom,rpmh.h>55 clock-controller@af00000 {56 compatible = "qcom,sm6350-dispcc";57 reg = <0x0af00000 0x20000>;58 clocks = <&rpmhcc RPMH_CXO_CLK>,59 <&gcc GCC_DISP_GPLL0_CLK>,60 <&dsi_phy 0>,61 <&dsi_phy 1>,62 <&dp_phy 0>,63 <&dp_phy 1>;64 clock-names = "bi_tcxo",65 "gcc_disp_gpll0_clk",66 "dsi0_phy_pll_out_byteclk",67 "dsi0_phy_pll_out_dsiclk",68 "dp_phy_pll_link_clk",69 "dp_phy_pll_vco_div_clk";70 #clock-cells = <1>;71 #reset-cells = <1>;72 #power-domain-cells = <1>;73 };74...75