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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on APQ80848 9maintainers:10 - Stephen Boyd <sboyd@kernel.org>11 - Taniya Das <quic_tdas@quicinc.com>12 13description: |14 Qualcomm global clock control module provides the clocks, resets and power15 domains on APQ8084.16 17 See also::18 include/dt-bindings/clock/qcom,gcc-apq8084.h19 include/dt-bindings/reset/qcom,gcc-apq8084.h20 21allOf:22 - $ref: qcom,gcc.yaml#23 24properties:25 compatible:26 const: qcom,gcc-apq808427 28 clocks:29 items:30 - description: XO source31 - description: Sleep clock source32 - description: UFS RX symbol 0 clock33 - description: UFS RX symbol 1 clock34 - description: UFS TX symbol 0 clock35 - description: UFS TX symbol 1 clock36 - description: SATA ASIC0 clock37 - description: SATA RX clock38 - description: PCIe PIPE clock39 40 clock-names:41 items:42 - const: xo43 - const: sleep_clk44 - const: ufs_rx_symbol_0_clk_src45 - const: ufs_rx_symbol_1_clk_src46 - const: ufs_tx_symbol_0_clk_src47 - const: ufs_tx_symbol_1_clk_src48 - const: sata_asic0_clk49 - const: sata_rx_clk50 - const: pcie_pipe51 52required:53 - compatible54 - '#power-domain-cells'55 56unevaluatedProperties: false57 58examples:59 - |60 /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */61 clock-controller@fc400000 {62 compatible = "qcom,gcc-apq8084";63 reg = <0xfc400000 0x4000>;64 #clock-cells = <1>;65 #reset-cells = <1>;66 #power-domain-cells = <1>;67 68 clocks = <&xo_board>,69 <&sleep_clk>,70 <&ufsphy 0>,71 <&ufsphy 1>,72 <&ufsphy 2>,73 <&ufsphy 3>,74 <&sata 0>,75 <&sata 1>,76 <&pcie_phy>;77 clock-names = "xo",78 "sleep_clk",79 "ufs_rx_symbol_0_clk_src",80 "ufs_rx_symbol_1_clk_src",81 "ufs_tx_symbol_0_clk_src",82 "ufs_tx_symbol_1_clk_src",83 "sata_asic0_clk",84 "sata_rx_clk",85 "pcie_pipe";86 };87...88