83 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Global Clock & Reset Controller on IPQ80648 9maintainers:10 - Ansuel Smith <ansuelsmth@gmail.com>11 12description: |13 Qualcomm global clock control module provides the clocks, resets and power14 domains on IPQ8064.15 16 See also::17 include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)18 include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)19 20allOf:21 - $ref: qcom,gcc.yaml#22 23properties:24 compatible:25 items:26 - const: qcom,gcc-ipq806427 - const: syscon28 29 clocks:30 minItems: 231 items:32 - description: PXO source33 - description: CXO source34 - description: PLL4 from LCC35 36 clock-names:37 minItems: 238 items:39 - const: pxo40 - const: cxo41 - const: pll442 43 thermal-sensor:44 type: object45 46 allOf:47 - $ref: /schemas/thermal/qcom-tsens.yaml#48 49 '#power-domain-cells': false50 51required:52 - compatible53 - clocks54 - clock-names55 56unevaluatedProperties: false57 58examples:59 - |60 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>61 #include <dt-bindings/interrupt-controller/arm-gic.h>62 63 gcc: clock-controller@900000 {64 compatible = "qcom,gcc-ipq8064", "syscon";65 reg = <0x00900000 0x4000>;66 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;67 clock-names = "pxo", "cxo", "pll4";68 #clock-cells = <1>;69 #reset-cells = <1>;70 71 tsens: thermal-sensor {72 compatible = "qcom,ipq8064-tsens";73 74 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;75 nvmem-cell-names = "calib", "calib_backup";76 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;77 interrupt-names = "uplow";78 79 #qcom,sensors = <11>;80 #thermal-sensor-cells = <1>;81 };82 };83